tools/litex_term: Add time.sleep on BridgeUART to avoid high CPU usage.

This commit is contained in:
Florent Kermarrec 2021-04-22 17:05:07 +02:00
parent 75045914b4
commit 0ed7852779
1 changed files with 1 additions and 0 deletions

View File

@ -122,6 +122,7 @@ class BridgeUART:
elif not self.rxempty.read(): elif not self.rxempty.read():
length = 1 length = 1
else: else:
time.sleep(1e-3)
continue continue
r = self.bus.read(self.rxtx.addr, length=length, burst="fixed") r = self.bus.read(self.rxtx.addr, length=length, burst="fixed")
for v in r: for v in r: