cores/cpu/json2dts: Add CPU_MMU config in cores and add initial NaxRisv support to json2dts.

Also do minor cleanups by regrouping CPU parameters at the top.
This commit is contained in:
Florent Kermarrec 2023-02-20 14:49:01 +01:00
parent 019fac5653
commit 0f000a0a90
4 changed files with 34 additions and 19 deletions

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@ -302,6 +302,7 @@ class NaxRiscv(CPU):
# Define ISA. # Define ISA.
soc.add_config("CPU_ISA", NaxRiscv.get_arch()) soc.add_config("CPU_ISA", NaxRiscv.get_arch())
soc.add_config("CPU_MMU", "sv39")
# Add PLIC Bus (AXILite Slave). # Add PLIC Bus (AXILite Slave).
self.plicbus = plicbus = axi.AXILiteInterface(address_width=32, data_width=32) self.plicbus = plicbus = axi.AXILiteInterface(address_width=32, data_width=32)

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@ -367,7 +367,8 @@ class Rocket(CPU):
# Define number of CPUs # Define number of CPUs
soc.add_config("CPU_COUNT", num_cores) soc.add_config("CPU_COUNT", num_cores)
soc.add_config("CPU_ISA", self.get_arch(self.variant)) soc.add_config("CPU_ISA", self.get_arch(self.variant))
soc.add_config("CPU_MMU", "sv39")
# Constants for Cache so we can add them in the DTS. # Constants for Cache so we can add them in the DTS.
soc.add_config("CPU_DCACHE_SIZE", 4096) # CHECKME: correct/hardwired? soc.add_config("CPU_DCACHE_SIZE", 4096) # CHECKME: correct/hardwired?

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@ -401,7 +401,9 @@ class VexRiscvSMP(CPU):
# Define number of CPUs # Define number of CPUs
soc.add_config("CPU_COUNT", VexRiscvSMP.cpu_count) soc.add_config("CPU_COUNT", VexRiscvSMP.cpu_count)
soc.add_config("CPU_ISA", VexRiscvSMP.get_arch()) soc.add_config("CPU_ISA", VexRiscvSMP.get_arch())
soc.add_config("CPU_MMU", "sv32")
# Constants for cache so we can add them in the DTS. # Constants for cache so we can add them in the DTS.
if (VexRiscvSMP.dcache_size > 0): if (VexRiscvSMP.dcache_size > 0):
soc.add_config("CPU_DCACHE_SIZE", VexRiscvSMP.dcache_size) soc.add_config("CPU_DCACHE_SIZE", VexRiscvSMP.dcache_size)

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@ -13,14 +13,28 @@ import argparse
import os import os
def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_device=None, polling=False): def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_device=None, polling=False):
kB = 1024 kB = 1024
mB = kB*1024 mB = kB*1024
cpu_name = d["constants"]["config_cpu_human_name"]
aliases = {} aliases = {}
# CPU Architectures ----------------------------------------------------------------------------
# CHECKME: Move to core and generate a constant for each CPU?
cpu_architectures = {
"mor1kx" : "or1k",
"marocchino" : "or1k",
"vexriscv smp-linux" : "riscv",
"rocketrv64[imac]" : "riscv",
"naxriscv" : "riscv",
}
# CPU Parameters -------------------------------------------------------------------------------
ncpus = int(d["constants"].get("config_cpu_count", 1))
cpu_name = d["constants"].get("config_cpu_human_name")
cpu_arch = cpu_architectures[cpu_name]
cpu_isa = d["constants"].get("config_cpu_isa", None)
cpu_mmu = d["constants"].get("config_cpu_mmu", None)
# Header --------------------------------------------------------------------------------------- # Header ---------------------------------------------------------------------------------------
dts = """ dts = """
/dts-v1/; /dts-v1/;
@ -32,19 +46,14 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
""" """
# Boot Arguments ------------------------------------------------------------------------------- # Boot Arguments -------------------------------------------------------------------------------
cpu_architectures = {
"mor1kx" : "or1k",
"marocchino" : "or1k",
"vexriscv smp-linux" : "riscv",
"rocketrv64[imac]" : "riscv",
}
default_initrd_start = { default_initrd_start = {
"or1k": 8*mB, "or1k": 8*mB,
"riscv": 16*mB, "riscv": 16*mB,
} }
default_initrd_size = 8*mB default_initrd_size = 8*mB
cpu_arch = cpu_architectures[cpu_name]
if initrd_start is None: if initrd_start is None:
initrd_start = default_initrd_start[cpu_arch] initrd_start = default_initrd_start[cpu_arch]
@ -122,9 +131,6 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
i_tlb_size = d["constants"]["config_cpu_itlb_size"], i_tlb_size = d["constants"]["config_cpu_itlb_size"],
i_tlb_ways = d["constants"]["config_cpu_itlb_ways"]) i_tlb_ways = d["constants"]["config_cpu_itlb_ways"])
# CPU(s) Count.
ncpus = int(d["constants"].get("config_cpu_count", 1))
# CPU(s) Topology. # CPU(s) Topology.
cpu_map = "" cpu_map = ""
if ncpus > 1: if ncpus > 1:
@ -152,7 +158,7 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
device_type = "cpu"; device_type = "cpu";
compatible = "riscv"; compatible = "riscv";
riscv,isa = "{cpu_isa}"; riscv,isa = "{cpu_isa}";
mmu-type = "riscv,sv32"; mmu-type = "riscv,{cpu_mmu}";
reg = <{cpu}>; reg = <{cpu}>;
clock-frequency = <{sys_clk_freq}>; clock-frequency = <{sys_clk_freq}>;
status = "okay"; status = "okay";
@ -164,14 +170,19 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
compatible = "riscv,cpu-intc"; compatible = "riscv,cpu-intc";
}}; }};
}}; }};
""".format(cpu=cpu, irq=cpu, sys_clk_freq=d["constants"]["config_clock_frequency"], cpu_isa=d["constants"]["config_cpu_isa"], cache_desc=cache_desc, tlb_desc=tlb_desc) """.format(cpu=cpu, irq=cpu,
sys_clk_freq = d["constants"]["config_clock_frequency"],
cpu_isa = cpu_isa,
cpu_mmu = cpu_mmu,
cache_desc = cache_desc,
tlb_desc = tlb_desc)
dts += """ dts += """
{cpu_map} {cpu_map}
}}; }};
""".format(cpu_map=cpu_map) """.format(cpu_map=cpu_map)
# Mor1kx # Or1k
# ------ # ----
elif cpu_arch == "or1k": elif cpu_arch == "or1k":
dts += """ dts += """
cpus {{ cpus {{