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fhdl/structure: add Memory.get_port API

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Sebastien Bourdeauducq 2012-11-23 19:17:49 +01:00
parent 9d3e218863
commit 0f6215a13a
1 changed files with 24 additions and 1 deletions
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25
migen/fhdl/structure.py
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@ -308,6 +308,7 @@ class Instance(HUID):
(READ_FIRST, WRITE_FIRST, NO_CHANGE) = range(3) (READ_FIRST, WRITE_FIRST, NO_CHANGE) = range(3)
# NOTE: Direct use of MemoryPort is deprecated. Use Memory.get_port() instead.
class MemoryPort: class MemoryPort:
def __init__(self, adr, dat_r, we=None, dat_w=None, def __init__(self, adr, dat_r, we=None, dat_w=None,
async_read=False, re=None, we_granularity=0, mode=WRITE_FIRST, async_read=False, re=None, we_granularity=0, mode=WRITE_FIRST,
@ -322,13 +323,35 @@ class MemoryPort:
self.mode = mode self.mode = mode
self.clock_domain = clock_domain self.clock_domain = clock_domain
# NOTE: ports parameter will be removed
class Memory(HUID): class Memory(HUID):
def __init__(self, width, depth, *ports, init=None): def __init__(self, width, depth, *ports, init=None):
super().__init__() super().__init__()
self.width = width self.width = width
self.depth = depth self.depth = depth
self.ports = ports self.ports = list(ports)
self.init = init self.init = init
def get_port(self, write_capable=False, async_read=False,
has_re=False, we_granularity=0, mode=WRITE_FIRST,
clock_domain="sys"):
adr = Signal(BV(bits_for(self.depth-1)))
dat_r = Signal(BV(self.width))
if write_capable:
we = Signal()
dat_w = Signal(BV(self.width))
else:
we = None
dat_w = None
if has_re:
re = Signal()
else:
re = None
mp = MemoryPort(adr, dat_r, we, dat_w,
async_read, re, we_granularity, mode,
clock_domain)
self.ports.append(mp)
return mp
# #