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Change to common isr handler

This commit is contained in:
Navaneeth 2021-10-19 07:14:36 +05:30
parent ef8bab4c11
commit 0fbaa51c71
4 changed files with 7 additions and 27 deletions
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2
litex/soc/cores/cpu/ibex/crt0.S
View File

@ -116,8 +116,6 @@ bss_loop:
j bss_loop
bss_done:
li t0, 0x7FFF0880 // enable external interrupts
csrs mie, t0
call main
infinit_loop:

5
litex/soc/cores/cpu/ibex/csr-defs.h
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@ -5,9 +5,10 @@
#define CSR_MSTATUS_MIE 0x8
#define CSR_IRQ_MASK 0x304
#define CSR_IRQ_MASK 0x304
#define CSR_IRQ_PENDING 0x344
#define FIRQ_OFFSET 16
#define CSR_DCACHE_INFO 0xCC0
#endif /* CSR_DEFS__H */

6
litex/soc/cores/cpu/ibex/irq.h
View File

@ -22,19 +22,19 @@ static inline unsigned int irq_getmask(void)
{
unsigned int mask;
asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK));
return mask;
return (mask >> FIRQ_OFFSET);
}
static inline void irq_setmask(unsigned int mask)
{
// asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask));
asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask << FIRQ_OFFSET));
}
static inline unsigned int irq_pending(void)
{
unsigned int pending;
asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING));
return pending;
return (pending >> FIRQ_OFFSET);
}
#ifdef __cplusplus

21
litex/soc/software/bios/isr.c
View File

@ -79,7 +79,7 @@ void isr(void)
void isr(void)
{
unsigned int cause = csrr(mcause) & IRQ_MASK;
puts("isr");
if (csrr(mcause) & 0x80000000) {
#ifndef UART_POLLING
if (cause == (UART_INTERRUPT+FIRQ_OFFSET)){
@ -102,25 +102,6 @@ void isr(void)
#endif
}
}
#elif defined(__ibex__)
#define FIRQ_OFFSET 16
#define IRQ_MASK 0x7FFFFFFF
void isr(void)
{
__attribute__((unused)) unsigned int irqs;
irqs = irq_pending() & irq_getmask();
#ifdef CSR_UART_BASE
#ifndef UART_POLLING
if(irqs & (1 << (UART_INTERRUPT+FIRQ_OFFSET)))
uart_isr();
#endif
#endif
}
#elif defined(__microwatt__)
void isr(uint64_t vec)