soc/cores/spi/SPIMaster: rewrite/simplify.
- Make sure MOSI is latched on start, MISO is stable during Xfer (last value). - Allow clk_divider down to 2. - improve test errors reporting with hex() on AssertEqual.
This commit is contained in:
Florent Kermarrec
parent
63c19ff45f
commit
100aa5a4ca
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@ -41,94 +41,96 @@ class SPIMaster(Module, AutoCSR):
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# # #
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done = Signal()
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bits = Signal(8)
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xfer = Signal()
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shift = Signal()
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clk_enable = Signal()
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cs_enable = Signal()
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count = Signal(max=data_width)
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mosi_latch = Signal()
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miso_latch = Signal()
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# Clock generation -------------------------------------------------------------------------
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clk_divider = Signal(16)
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clk_rise = Signal()
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clk_fall = Signal()
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self.comb += clk_rise.eq(clk_divider == (self.clk_divider[1:] - 1))
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self.comb += clk_fall.eq(clk_divider == (self.clk_divider - 1))
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self.sync += [
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If(clk_rise, pads.clk.eq(xfer)),
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If(clk_fall, pads.clk.eq(0)),
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If(clk_fall,
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clk_divider.eq(0)
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).Else(
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clk_divider.eq(clk_divider + 1)
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clk_divider.eq(clk_divider + 1),
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If(clk_rise,
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pads.clk.eq(clk_enable),
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).Elif(clk_fall,
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clk_divider.eq(0),
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pads.clk.eq(0),
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)
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]
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self.comb += clk_rise.eq(clk_divider == (self.clk_divider[1:] - 1))
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self.comb += clk_fall.eq(clk_divider == (self.clk_divider - 1))
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# Control FSM ------------------------------------------------------------------------------
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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done.eq(1),
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self.done.eq(1),
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If(self.start,
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NextValue(bits, 0),
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NextState("WAIT-CLK-FALL")
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self.done.eq(0),
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mosi_latch.eq(1),
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NextState("START")
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)
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)
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fsm.act("WAIT-CLK-FALL",
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fsm.act("START",
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NextValue(count, 0),
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If(clk_fall,
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NextState("XFER")
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cs_enable.eq(1),
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NextState("RUN")
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)
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)
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fsm.act("XFER",
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If(bits == self.length,
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NextState("END")
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).Elif(clk_fall,
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NextValue(bits, bits + 1)
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),
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xfer.eq(1),
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shift.eq(1)
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fsm.act("RUN",
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clk_enable.eq(1),
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cs_enable.eq(1),
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If(clk_fall,
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NextValue(count, count + 1),
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If(count == (self.length - 1),
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NextState("STOP")
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)
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)
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)
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fsm.act("END",
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fsm.act("STOP",
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cs_enable.eq(1),
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If(clk_rise,
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miso_latch.eq(1),
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self.irq.eq(1),
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NextState("IDLE")
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),
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shift.eq(1),
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self.irq.eq(1)
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)
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)
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self.sync += self.done.eq(done & ~self.start)
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# Chip Select generation -------------------------------------------------------------------
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if hasattr(pads, "cs_n"):
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for i in range(len(pads.cs_n)):
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self.comb += pads.cs_n[i].eq(~self.cs[i] | ~xfer)
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self.sync += pads.cs_n[i].eq(~self.cs[i] | ~cs_enable)
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# Master Out Slave In (MOSI) generation (generated on spi_clk falling edge) ----------------
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mosi_data = Array(self.mosi[i] for i in range(data_width))
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mosi_bit = Signal(max=data_width)
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mosi_data = Signal(data_width)
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mosi_array = Array(mosi_data[i] for i in range(data_width))
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mosi_sel = Signal(max=data_width)
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self.sync += [
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If(self.start,
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mosi_bit.eq(self.length - 1 if mode == "aligned" else data_width - 1),
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).Elif(clk_rise & shift,
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mosi_bit.eq(mosi_bit - 1)
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If(mosi_latch,
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mosi_data.eq(self.mosi),
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mosi_sel.eq((self.length-1) if mode == "aligned" else (data_width-1)),
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).Elif(clk_fall,
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If(cs_enable, pads.mosi.eq(mosi_array[mosi_sel])),
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mosi_sel.eq(mosi_sel - 1)
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),
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If(clk_fall,
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pads.mosi.eq(mosi_data[mosi_bit])
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)
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]
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# Master In Slave Out (MISO) capture (captured on spi_clk rising edge) --------------------
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miso = Signal()
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miso_data = Signal(data_width)
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self.sync += [
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If(clk_rise & shift,
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If(clk_rise,
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If(self.loopback,
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miso.eq(pads.mosi)
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miso_data.eq(Cat(pads.mosi, miso_data))
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).Else(
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miso.eq(pads.miso)
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miso_data.eq(Cat(pads.miso, miso_data))
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)
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),
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If(clk_fall & shift,
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miso_data.eq(Cat(miso, miso_data))
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),
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If(done, self.miso.eq(miso_data)),
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)
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]
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self.sync += If(miso_latch, self.miso.eq(miso_data))
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def add_csr(self, with_cs=True, with_loopback=True):
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self._control = CSRStorage(fields=[
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@ -16,6 +16,7 @@ class TestSPI(unittest.TestCase):
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def test_spi_master_xfer_loopback_32b_32b(self):
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def generator(dut):
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yield dut.loopback.eq(1)
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yield dut.clk_divider.eq(2)
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yield dut.mosi.eq(0xdeadbeef)
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yield dut.length.eq(32)
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yield dut.start.eq(1)
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@ -24,7 +25,8 @@ class TestSPI(unittest.TestCase):
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yield
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while (yield dut.done) == 0:
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yield
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self.assertEqual((yield dut.miso), 0xdeadbeef)
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yield
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self.assertEqual(hex((yield dut.miso)), hex(0xdeadbeef))
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dut = SPIMaster(pads=None, data_width=32, sys_clk_freq=100e6, spi_clk_freq=5e6, with_csr=False)
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run_simulation(dut, generator(dut))
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@ -40,7 +42,8 @@ class TestSPI(unittest.TestCase):
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yield
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while (yield dut.done) == 0:
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yield
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self.assertEqual((yield dut.miso), 0xbeef)
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yield
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self.assertEqual(hex((yield dut.miso)), hex(0xbeef))
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dut = SPIMaster(pads=None, data_width=32, sys_clk_freq=100e6, spi_clk_freq=5e6, with_csr=False, mode="aligned")
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run_simulation(dut, generator(dut))
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@ -59,6 +62,8 @@ class TestSPI(unittest.TestCase):
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self.submodules.slave = SPISlave(pads, data_width=32)
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def master_generator(dut):
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for i in range(8):
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yield
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yield dut.master.mosi.eq(0xdeadbeef)
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yield dut.master.length.eq(32)
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yield dut.master.start.eq(1)
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@ -67,15 +72,19 @@ class TestSPI(unittest.TestCase):
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yield
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while (yield dut.master.done) == 0:
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yield
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self.assertEqual((yield dut.master.miso), 0x12345678)
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yield
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self.assertEqual(hex((yield dut.master.miso)), hex(0x12345678))
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def slave_generator(dut):
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for i in range(8):
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yield
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yield dut.slave.miso.eq(0x12345678)
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while (yield dut.slave.start) == 0:
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yield
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while (yield dut.slave.done) == 0:
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yield
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self.assertEqual((yield dut.slave.mosi), 0xdeadbeef)
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yield
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self.assertEqual(hex((yield dut.slave.mosi)), hex(0xdeadbeef))
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self.assertEqual((yield dut.slave.length), 32)
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dut = DUT()
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