Merge pull request #2097 from trabucayre/build_diamond_addition

Build diamond addition

litex/build/lattice/diamond.py

@@ -36,6 +36,7 @@ class LatticeDiamondToolchain(GenericToolchain):
 
     def __init__(self):
         super().__init__()
+        self.additional_ldf_commands = []
 
     def build(self, platform, fragment,
         timingstrict   = False,
@@ -116,9 +117,20 @@ class LatticeDiamondToolchain(GenericToolchain):
         for filename, language, library, *copy in self.platform.sources:
             tcl.append("prj_src add \"{}\" -work {}".format(tcl_path(filename), library))
 
+        # Add IPs
+        for filename in self.platform.ips:
+            tcl.append("prj_src add \"{}\" -work {}".format(tcl_path(filename), library))
+
+        # Add Strategy
+        for filename, strategy_name in self.platform.strategy:
+            tcl.append("prj_strgy import -name {} -file {}".format(strategy_name, tcl_path(filename)))
+
         # Set top level
         tcl.append("prj_impl option top \"{}\"".format(self._build_name))
 
+        # Add additional commands
+        tcl += self.additional_ldf_commands
+
         # Save project
         tcl.append("prj_project save")
 

litex/build/lattice/platform.py

@@ -5,6 +5,8 @@
 # Copyright (c) 2017 William D. Jones <thor0505@comcast.net>
 # SPDX-License-Identifier: BSD-2-Clause
 
+import os
+
 from litex.build.generic_platform import GenericPlatform
 from litex.build.lattice import common, diamond, icestorm, trellis, radiant, oxide
 
@@ -21,6 +23,8 @@ class LatticePlatform(GenericPlatform):
 
     def __init__(self, *args, toolchain="diamond", **kwargs):
         GenericPlatform.__init__(self, *args, **kwargs)
+        self.ips      = set()
+        self.strategy = set()
         if toolchain == "diamond":
             self.toolchain = diamond.LatticeDiamondToolchain()
         elif toolchain == "trellis":
@@ -35,6 +39,12 @@ class LatticePlatform(GenericPlatform):
         else:
             raise ValueError(f"Unknown toolchain {toolchain}")
 
+    def add_ip(self, filename):
+        self.ips.add((os.path.abspath(filename)))
+
+    def add_strategy(self, filename, strategy_name):
+        self.strategy.add((os.path.abspath(filename), strategy_name))
+
     def get_verilog(self, *args, special_overrides=dict(), **kwargs):
         so = dict()  # No common overrides between ECP5 and iCE40.
         so.update(self.toolchain.special_overrides)

litex/soc/cores/jtag.py

@@ -379,7 +379,7 @@ class ECP5JTAG(LiteXModule):
             new_tck = Signal()
             self.specials += Instance("LUT4",
                 attr   = {"keep"},
-                p_INIT = 2,
+                p_init = 2,
                 i_A = tck,
                 i_B = 0,
                 i_C = 0,