soc/integration: add common.py and move helpers from soc_core to it
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# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import os
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import math
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import json
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import time
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import struct
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import datetime
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from migen import *
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def mem_decoder(address, size=0x10000000):
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address &= ~0x80000000
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size = 2**log2_int(size, False)
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assert (address & (size - 1)) == 0
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address >>= 2 # bytes to words aligned
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size >>= 2 # bytes to words aligned
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return lambda a: (a[log2_int(size):-1] == (address >> log2_int(size)))
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def get_version(with_time=True):
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if with_time:
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return datetime.datetime.fromtimestamp(
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time.time()).strftime("%Y-%m-%d %H:%M:%S")
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else:
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return datetime.datetime.fromtimestamp(
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time.time()).strftime("%Y-%m-%d")
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def get_mem_data(filename_or_regions, endianness="big", mem_size=None):
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# create memory regions
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if isinstance(filename_or_regions, dict):
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regions = filename_or_regions
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else:
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filename = filename_or_regions
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_, ext = os.path.splitext(filename)
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if ext == ".json":
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f = open(filename, "r")
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regions = json.load(f)
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f.close()
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else:
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regions = {filename: "0x00000000"}
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# determine data_size
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data_size = 0
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for filename, base in regions.items():
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data_size = max(int(base, 16) + os.path.getsize(filename), data_size)
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assert data_size > 0
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if mem_size is not None:
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assert data_size < mem_size, (
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"file is too big: {}/{} bytes".format(
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data_size, mem_size))
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# fill data
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data = [0]*math.ceil(data_size/4)
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for filename, base in regions.items():
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with open(filename, "rb") as f:
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i = 0
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while True:
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w = f.read(4)
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if not w:
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break
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if len(w) != 4:
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for _ in range(len(w), 4):
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w += b'\x00'
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if endianness == "little":
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data[int(base, 16)//4 + i] = struct.unpack("<I", w)[0]
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else:
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data[int(base, 16)//4 + i] = struct.unpack(">I", w)[0]
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i += 1
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return data
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@ -13,12 +13,7 @@
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# License: BSD
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import os
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import struct
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import inspect
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import json
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import math
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import datetime
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import time
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from operator import itemgetter
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from migen import *
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@ -29,7 +24,7 @@ from litex.soc.cores import identifier, timer, uart
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from litex.soc.cores import cpu
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from litex.soc.interconnect.csr import *
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from litex.soc.interconnect import wishbone, csr_bus, wishbone2csr
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from litex.soc.integration.common import *
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__all__ = [
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"mem_decoder",
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@ -42,67 +37,6 @@ __all__ = [
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"soc_mini_argdict",
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]
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# Helpers ------------------------------------------------------------------------------------------
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def version(with_time=True):
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if with_time:
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return datetime.datetime.fromtimestamp(
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time.time()).strftime("%Y-%m-%d %H:%M:%S")
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else:
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return datetime.datetime.fromtimestamp(
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time.time()).strftime("%Y-%m-%d")
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def get_mem_data(filename_or_regions, endianness="big", mem_size=None):
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# create memory regions
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if isinstance(filename_or_regions, dict):
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regions = filename_or_regions
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else:
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filename = filename_or_regions
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_, ext = os.path.splitext(filename)
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if ext == ".json":
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f = open(filename, "r")
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regions = json.load(f)
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f.close()
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else:
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regions = {filename: "0x00000000"}
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# determine data_size
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data_size = 0
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for filename, base in regions.items():
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data_size = max(int(base, 16) + os.path.getsize(filename), data_size)
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assert data_size > 0
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if mem_size is not None:
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assert data_size < mem_size, (
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"file is too big: {}/{} bytes".format(
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data_size, mem_size))
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# fill data
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data = [0]*math.ceil(data_size/4)
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for filename, base in regions.items():
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with open(filename, "rb") as f:
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i = 0
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while True:
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w = f.read(4)
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if not w:
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break
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if len(w) != 4:
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for _ in range(len(w), 4):
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w += b'\x00'
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if endianness == "little":
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data[int(base, 16)//4 + i] = struct.unpack("<I", w)[0]
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else:
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data[int(base, 16)//4 + i] = struct.unpack(">I", w)[0]
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i += 1
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return data
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def mem_decoder(address, size=0x10000000):
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address &= ~0x80000000
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size = 2**log2_int(size, False)
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assert (address & (size - 1)) == 0
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address >>= 2 # bytes to words aligned
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size >>= 2 # bytes to words aligned
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return lambda a: (a[log2_int(size):-1] == (address >> log2_int(size)))
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# SoCController ------------------------------------------------------------------------------------
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class SoCController(Module, AutoCSR):
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@ -307,7 +241,7 @@ class SoCCore(Module):
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# Add Identifier
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if ident:
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if ident_version:
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ident = ident + " " + version()
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ident = ident + " " + get_version()
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self.submodules.identifier = identifier.Identifier(ident)
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self.add_csr("identifier_mem", allow_user_defined=True)
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self.config["CLOCK_FREQUENCY"] = int(clk_freq)
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