soc/integration: add common.py and move helpers from soc_core to it

This commit is contained in:
Florent Kermarrec 2019-09-29 14:22:26 +02:00
parent 68ba1c60be
commit 101f1b1cef
2 changed files with 72 additions and 68 deletions

View File

@ -0,0 +1,70 @@
# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
import os
import math
import json
import time
import struct
import datetime
from migen import *
def mem_decoder(address, size=0x10000000):
address &= ~0x80000000
size = 2**log2_int(size, False)
assert (address & (size - 1)) == 0
address >>= 2 # bytes to words aligned
size >>= 2 # bytes to words aligned
return lambda a: (a[log2_int(size):-1] == (address >> log2_int(size)))
def get_version(with_time=True):
if with_time:
return datetime.datetime.fromtimestamp(
time.time()).strftime("%Y-%m-%d %H:%M:%S")
else:
return datetime.datetime.fromtimestamp(
time.time()).strftime("%Y-%m-%d")
def get_mem_data(filename_or_regions, endianness="big", mem_size=None):
# create memory regions
if isinstance(filename_or_regions, dict):
regions = filename_or_regions
else:
filename = filename_or_regions
_, ext = os.path.splitext(filename)
if ext == ".json":
f = open(filename, "r")
regions = json.load(f)
f.close()
else:
regions = {filename: "0x00000000"}
# determine data_size
data_size = 0
for filename, base in regions.items():
data_size = max(int(base, 16) + os.path.getsize(filename), data_size)
assert data_size > 0
if mem_size is not None:
assert data_size < mem_size, (
"file is too big: {}/{} bytes".format(
data_size, mem_size))
# fill data
data = [0]*math.ceil(data_size/4)
for filename, base in regions.items():
with open(filename, "rb") as f:
i = 0
while True:
w = f.read(4)
if not w:
break
if len(w) != 4:
for _ in range(len(w), 4):
w += b'\x00'
if endianness == "little":
data[int(base, 16)//4 + i] = struct.unpack("<I", w)[0]
else:
data[int(base, 16)//4 + i] = struct.unpack(">I", w)[0]
i += 1
return data

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@ -13,12 +13,7 @@
# License: BSD
import os
import struct
import inspect
import json
import math
import datetime
import time
from operator import itemgetter
from migen import *
@ -29,7 +24,7 @@ from litex.soc.cores import identifier, timer, uart
from litex.soc.cores import cpu
from litex.soc.interconnect.csr import *
from litex.soc.interconnect import wishbone, csr_bus, wishbone2csr
from litex.soc.integration.common import *
__all__ = [
"mem_decoder",
@ -42,67 +37,6 @@ __all__ = [
"soc_mini_argdict",
]
# Helpers ------------------------------------------------------------------------------------------
def version(with_time=True):
if with_time:
return datetime.datetime.fromtimestamp(
time.time()).strftime("%Y-%m-%d %H:%M:%S")
else:
return datetime.datetime.fromtimestamp(
time.time()).strftime("%Y-%m-%d")
def get_mem_data(filename_or_regions, endianness="big", mem_size=None):
# create memory regions
if isinstance(filename_or_regions, dict):
regions = filename_or_regions
else:
filename = filename_or_regions
_, ext = os.path.splitext(filename)
if ext == ".json":
f = open(filename, "r")
regions = json.load(f)
f.close()
else:
regions = {filename: "0x00000000"}
# determine data_size
data_size = 0
for filename, base in regions.items():
data_size = max(int(base, 16) + os.path.getsize(filename), data_size)
assert data_size > 0
if mem_size is not None:
assert data_size < mem_size, (
"file is too big: {}/{} bytes".format(
data_size, mem_size))
# fill data
data = [0]*math.ceil(data_size/4)
for filename, base in regions.items():
with open(filename, "rb") as f:
i = 0
while True:
w = f.read(4)
if not w:
break
if len(w) != 4:
for _ in range(len(w), 4):
w += b'\x00'
if endianness == "little":
data[int(base, 16)//4 + i] = struct.unpack("<I", w)[0]
else:
data[int(base, 16)//4 + i] = struct.unpack(">I", w)[0]
i += 1
return data
def mem_decoder(address, size=0x10000000):
address &= ~0x80000000
size = 2**log2_int(size, False)
assert (address & (size - 1)) == 0
address >>= 2 # bytes to words aligned
size >>= 2 # bytes to words aligned
return lambda a: (a[log2_int(size):-1] == (address >> log2_int(size)))
# SoCController ------------------------------------------------------------------------------------
class SoCController(Module, AutoCSR):
@ -307,7 +241,7 @@ class SoCCore(Module):
# Add Identifier
if ident:
if ident_version:
ident = ident + " " + version()
ident = ident + " " + get_version()
self.submodules.identifier = identifier.Identifier(ident)
self.add_csr("identifier_mem", allow_user_defined=True)
self.config["CLOCK_FREQUENCY"] = int(clk_freq)