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soc/add_spi_flash: Pass device to LiteSPIPHY for proper clk primitive instantiation.

This commit is contained in:
Florent Kermarrec 2021-09-02 11:26:15 +02:00
parent 315fbe18cb
commit 103b108ea8
1 changed files with 1 additions and 1 deletions
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litex/soc/integration/soc.py
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@ -1511,7 +1511,7 @@ class LiteXSoC(SoC):
self.check_if_exists(name + "_phy") self.check_if_exists(name + "_phy")
self.check_if_exists(name + "_mmap") self.check_if_exists(name + "_mmap")
spiflash_pads = self.platform.request(name if mode == "1x" else name + mode) spiflash_pads = self.platform.request(name if mode == "1x" else name + mode)
spiflash_phy = LiteSPIPHY(spiflash_pads, module, default_divisor=int(self.sys_clk_freq/clk_freq)) spiflash_phy = LiteSPIPHY(spiflash_pads, module, device=self.platform.device, default_divisor=int(self.sys_clk_freq/clk_freq))
spiflash_core = LiteSPI(spiflash_phy, clk_freq=clk_freq, mmap_endianness=self.cpu.endianness, **kwargs) spiflash_core = LiteSPI(spiflash_phy, clk_freq=clk_freq, mmap_endianness=self.cpu.endianness, **kwargs)
setattr(self.submodules, name + "_phy", spiflash_phy) setattr(self.submodules, name + "_phy", spiflash_phy)
setattr(self.submodules, name + "_core", spiflash_core) setattr(self.submodules, name + "_core", spiflash_core)