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integration/soc/add_sdram: Use new AXIUpConverter when up-converting is required (Instead of going through Wishbone).

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This commit is contained in:
Florent Kermarrec 2022-02-17 17:23:16 +01:00
parent ea49be9302
commit 1052584cf7
1 changed files with 16 additions and 7 deletions
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23
litex/soc/integration/soc.py
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@ -1358,17 +1358,25 @@ class LiteXSoC(SoC):
if isinstance(mem_bus, axi.AXIInterface):
# If same data_width, connect it directly.
if port.data_width == mem_bus.data_width:
self.logger.info("Matching AXI MEM data width ({})\n".format(port.data_width))
self.submodules += LiteDRAMAXI2Native(
axi = mem_bus,
port = port,
base_address = self.bus.regions["main_ram"].origin)
# If different data_width, do the adaptation and connect it via Wishbone.
base_address = self.bus.regions["main_ram"].origin
)
# UpConvert.
elif port.data_width > mem_bus.data_width:
axi_port = axi.AXIInterface(data_width=port.data_width, id_width=8) # FIXME: id_width.
self.submodules += axi.AXIUpConverter(
axi_from = mem_bus,
axi_to = axi_port,
)
self.submodules += LiteDRAMAXI2Native(
axi = axi_port,
port = port,
base_address = self.bus.regions["main_ram"].origin
)
# DownConvert. FIXME: Pass through Wishbone for now, create/use native AXI converter.
else:
self.logger.info("Converting MEM data width: {} to {} via Wishbone".format(
port.data_width,
mem_bus.data_width))
# FIXME: Replace WB data-width converter with native AXI converter.
mem_wb = wishbone.Interface(
data_width = self.cpu.mem_axi.data_width,
adr_width = 32-log2_int(mem_bus.data_width//8))
@ -1383,6 +1391,7 @@ class LiteXSoC(SoC):
port = port,
base_address = self.bus.regions["main_ram"].origin)
self.submodules += wishbone.Converter(mem_wb, litedram_wb)
# Check if bus is a Native bus and connect it.
if isinstance(mem_bus, LiteDRAMNativePort):
# If same data_width, connect it directly.