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cores/video/VideoPHYs: Use IO primitives.

This commit is contained in:
Florent Kermarrec 2021-03-04 18:22:34 +01:00
parent 82d0ecd7bd
commit 10d87e4138
1 changed files with 33 additions and 30 deletions
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63
litex/soc/cores/video.py
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@ -13,6 +13,8 @@ from migen.genlib.cdc import MultiReg
from litex.soc.interconnect.csr import * from litex.soc.interconnect.csr import *
from litex.soc.interconnect import stream from litex.soc.interconnect import stream
from litex.build.io import SDROutput, DDROutput
# Video Constants ---------------------------------------------------------------------------------- # Video Constants ----------------------------------------------------------------------------------
hbits = 12 hbits = 12
@ -617,30 +619,32 @@ class VideoFrameBuffer(Module, AutoCSR):
# Video PHYs --------------------------------------------------------------------------------------- # Video PHYs ---------------------------------------------------------------------------------------
class VideoDVIPHY(Module): class VideoDVIPHY(Module):
def __init__(self, pads, clock_domain="sys"): def __init__(self, pads, clock_domain="sys", with_clk_ddr_output=True):
self.sink = sink = stream.Endpoint(video_data_layout) self.sink = sink = stream.Endpoint(video_data_layout)
# # # # # #
# FIXME: Use IOs primitives. # Always ack Sink, no backpressure.
self.comb += sink.ready.eq(1)
self.comb += [ # Drive DVI Clk.
# Always ack Sink, no backpressure. if with_clk_ddr_output:
sink.ready.eq(1), self.specials += DDROutput(i1=1, i2=0, o=pads.clk, clk=ClockSignal(clock_domain))
else:
self.comb += pads.clk.eq(ClockSignal(clock_domain))
# Drive DVI Clk. # Drive DVI Controls.
pads.clk.eq(ClockSignal(clock_domain)), self.specials += SDROutput(i=sink.de, o=pads.de, clk=ClockSignal(clock_domain))
self.specials += SDROutput(i=sink.hsync, o=pads.hsync, clk=ClockSignal(clock_domain))
self.specials += SDROutput(i=sink.vsync, o=pads.vsync, clk=ClockSignal(clock_domain))
# Drive DVI Controls. # Drive DVI Datas.
pads.de.eq(sink.de), cbits = len(pads.r)
pads.hsync.eq(sink.hsync), cshift = (8 - cbits)
pads.vsync.eq(sink.vsync), for i in range(cbits):
self.specials += SDROutput(i=sink.r[cshift + i], o=pads.r[i], clk=ClockSignal(clock_domain))
# Drive DVI Datas. self.specials += SDROutput(i=sink.g[cshift + i], o=pads.g[i], clk=ClockSignal(clock_domain))
pads.r.eq(sink.r[8-len(pads.r):]), self.specials += SDROutput(i=sink.b[cshift + i], o=pads.b[i], clk=ClockSignal(clock_domain))
pads.g.eq(sink.g[8-len(pads.g):]),
pads.b.eq(sink.b[8-len(pads.b):]),
]
class VideoVGAPHY(Module): class VideoVGAPHY(Module):
@ -649,18 +653,17 @@ class VideoVGAPHY(Module):
# # # # # #
# FIXME: Use IOs primitives. # Always ack Sink, no backpressure.
self.comb += sink.ready.eq(1)
self.comb += [ # Drive VGA Conrols.
# Always ack Sink, no backpressure. self.specials += SDROutput(i=~sink.hsync, o=pads.hsync_n, clk=ClockSignal(clock_domain))
sink.ready.eq(1), self.specials += SDROutput(i=~sink.vsync, o=pads.vsync_n, clk=ClockSignal(clock_domain))
# Drive DVI Controls. # Drive VGA Datas.
pads.hsync_n.eq(~sink.hsync), cbits = len(pads.r)
pads.vsync_n.eq(~sink.vsync), cshift = (8 - cbits)
for i in range(cbits):
# Drive DVI Datas. self.specials += SDROutput(i=sink.r[cshift + i], o=pads.r[i], clk=ClockSignal(clock_domain))
pads.r.eq(sink.r[8-len(pads.r):]), self.specials += SDROutput(i=sink.g[cshift + i], o=pads.g[i], clk=ClockSignal(clock_domain))
pads.g.eq(sink.g[8-len(pads.g):]), self.specials += SDROutput(i=sink.b[cshift + i], o=pads.b[i], clk=ClockSignal(clock_domain))
pads.b.eq(sink.b[8-len(pads.b):]),
]