cores/video/VideoPHYs: Use IO primitives.
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@ -13,6 +13,8 @@ from migen.genlib.cdc import MultiReg
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from litex.soc.interconnect.csr import *
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from litex.soc.interconnect import stream
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from litex.build.io import SDROutput, DDROutput
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# Video Constants ----------------------------------------------------------------------------------
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hbits = 12
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@ -617,30 +619,32 @@ class VideoFrameBuffer(Module, AutoCSR):
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# Video PHYs ---------------------------------------------------------------------------------------
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class VideoDVIPHY(Module):
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def __init__(self, pads, clock_domain="sys"):
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def __init__(self, pads, clock_domain="sys", with_clk_ddr_output=True):
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self.sink = sink = stream.Endpoint(video_data_layout)
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# # #
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# FIXME: Use IOs primitives.
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# Always ack Sink, no backpressure.
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self.comb += sink.ready.eq(1)
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self.comb += [
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# Always ack Sink, no backpressure.
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sink.ready.eq(1),
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# Drive DVI Clk.
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if with_clk_ddr_output:
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self.specials += DDROutput(i1=1, i2=0, o=pads.clk, clk=ClockSignal(clock_domain))
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else:
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self.comb += pads.clk.eq(ClockSignal(clock_domain))
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# Drive DVI Clk.
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pads.clk.eq(ClockSignal(clock_domain)),
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# Drive DVI Controls.
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self.specials += SDROutput(i=sink.de, o=pads.de, clk=ClockSignal(clock_domain))
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self.specials += SDROutput(i=sink.hsync, o=pads.hsync, clk=ClockSignal(clock_domain))
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self.specials += SDROutput(i=sink.vsync, o=pads.vsync, clk=ClockSignal(clock_domain))
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# Drive DVI Controls.
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pads.de.eq(sink.de),
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pads.hsync.eq(sink.hsync),
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pads.vsync.eq(sink.vsync),
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# Drive DVI Datas.
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pads.r.eq(sink.r[8-len(pads.r):]),
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pads.g.eq(sink.g[8-len(pads.g):]),
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pads.b.eq(sink.b[8-len(pads.b):]),
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]
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# Drive DVI Datas.
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cbits = len(pads.r)
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cshift = (8 - cbits)
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for i in range(cbits):
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self.specials += SDROutput(i=sink.r[cshift + i], o=pads.r[i], clk=ClockSignal(clock_domain))
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self.specials += SDROutput(i=sink.g[cshift + i], o=pads.g[i], clk=ClockSignal(clock_domain))
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self.specials += SDROutput(i=sink.b[cshift + i], o=pads.b[i], clk=ClockSignal(clock_domain))
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class VideoVGAPHY(Module):
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@ -649,18 +653,17 @@ class VideoVGAPHY(Module):
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# # #
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# FIXME: Use IOs primitives.
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# Always ack Sink, no backpressure.
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self.comb += sink.ready.eq(1)
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self.comb += [
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# Always ack Sink, no backpressure.
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sink.ready.eq(1),
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# Drive VGA Conrols.
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self.specials += SDROutput(i=~sink.hsync, o=pads.hsync_n, clk=ClockSignal(clock_domain))
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self.specials += SDROutput(i=~sink.vsync, o=pads.vsync_n, clk=ClockSignal(clock_domain))
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# Drive DVI Controls.
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pads.hsync_n.eq(~sink.hsync),
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pads.vsync_n.eq(~sink.vsync),
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# Drive DVI Datas.
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pads.r.eq(sink.r[8-len(pads.r):]),
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pads.g.eq(sink.g[8-len(pads.g):]),
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pads.b.eq(sink.b[8-len(pads.b):]),
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]
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# Drive VGA Datas.
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cbits = len(pads.r)
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cshift = (8 - cbits)
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for i in range(cbits):
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self.specials += SDROutput(i=sink.r[cshift + i], o=pads.r[i], clk=ClockSignal(clock_domain))
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self.specials += SDROutput(i=sink.g[cshift + i], o=pads.g[i], clk=ClockSignal(clock_domain))
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self.specials += SDROutput(i=sink.b[cshift + i], o=pads.b[i], clk=ClockSignal(clock_domain))
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