add need_reset from controller to request system reset when SATA is not locked

lib/sata/common.py

@@ -210,6 +210,18 @@ class Counter(Module):
 		self.width = flen(self.value)
 		self.sync += self.value.eq(self.value+1)
 
+@DecorateModule(InsertReset)
+@DecorateModule(InsertCE)
+class Timeout(Module):
+	def __init__(self, length):
+		self.reached = Signal()
+		###
+		value = Signal(max=length)
+		self.sync += value.eq(value+1)
+		self.comb += [
+			self.reached.eq(value == length)
+		]
+
 # XXX use ModuleDecorator
 class BufferizeEndpoints(Module):
 	def __init__(self, decorated, *args):

lib/sata/phy/ctrl.py

@@ -24,6 +24,7 @@ class SATAPHYHostCtrlTimeout(Module):
 class SATAPHYHostCtrl(Module):
 	def __init__(self, trx, crg, clk_freq):
 		self.ready = Signal()
+		self.need_reset = Signal()
 		self.sink = sink = Sink(phy_description(32))
 		self.source = source = Source(phy_description(32))
 
@@ -144,6 +145,12 @@ class SATAPHYHostCtrl(Module):
 			self.ready.eq(1),
 		)
 
+		self.reset_timeout = Timeout(clk_freq//16)
+		self.comb += [
+			self.reset_timeout.ce.eq(~self.ready),
+			self.need_reset.eq(self.reset_timeout.reached)
+		]
+
 		self.comb +=  \
 			align_detect.eq(self.sink.stb & (self.sink.data == primitives["ALIGN"]))
 		self.sync += \
@@ -157,6 +164,7 @@ class SATAPHYHostCtrl(Module):
 				)
 			)
 
+# Note : Tested only in simulation
 class SATAPHYDeviceCtrl(Module):
 	def __init__(self, trx, crg, clk_freq):
 		self.ready = Signal()

platforms/kc705.py

@@ -129,8 +129,8 @@ def Platform(*args, toolchain="vivado", programmer="xc3sprog", **kwargs):
 				pass
 			self.add_platform_command("""
 create_clock -name sys_clk -period 6 [get_nets sys_clk]
-create_clock -name sata_rx_clk -period 6.66 [get_nets sata_rx_clk]
-create_clock -name sata_tx_clk -period 6.66 [get_nets sata_tx_clk]
+create_clock -name sata_rx_clk -period 3.33 [get_nets sata_rx_clk]
+create_clock -name sata_tx_clk -period 3.33 [get_nets sata_tx_clk]
 
 set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_rx_clk]
 set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_tx_clk]

targets/test.py

@@ -20,7 +20,7 @@ from migen.genlib.cdc import *
 class _CRG(Module):
 	def __init__(self, platform):
 		self.cd_sys = ClockDomain()
-		self.cd_por = ClockDomain(reset_less=True)
+		self.sata_reset = Signal()
 
 		clk200 = platform.request("clk200")
 		clk200_se = Signal()
@@ -50,7 +50,7 @@ class _CRG(Module):
 				p_CLKOUT4_DIVIDE=2, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4=
 			),
 			Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
-			AsyncResetSynchronizer(self.cd_sys, ~pll_locked | platform.request("cpu_reset")),
+			AsyncResetSynchronizer(self.cd_sys, ~pll_locked | platform.request("cpu_reset") | self.sata_reset),
 		]
 
 class UART2WB(Module):
@@ -114,7 +114,7 @@ class SimDesign(UART2WB):
 		UART2WB.__init__(self, platform, clk_freq)
 		self.crg = _CRG(platform)
 
-		self.sata_phy_host = SATAPHY(platform.request("sata_host"), clk_freq, host=True)
+		sata_phy_host = SATAPHY(platform.request("sata_host"), clk_freq, host=True)
 		self.comb += [
 			self.sata_phy_host.sink.stb.eq(1),
 			self.sata_phy_host.sink.data.eq(primitives["SYNC"]),
@@ -169,7 +169,8 @@ class TestDesign(UART2WB, AutoCSR):
 		UART2WB.__init__(self, platform, clk_freq)
 		self.crg = _CRG(platform)
 
-		self.sata_phy = SATAPHY(platform.request("sata_host"), clk_freq, speed="SATA2")
+		self.sata_phy = SATAPHY(platform.request("sata_host"), clk_freq, speed="SATA3")
+		self.comb += self.crg.sata_reset.eq(self.sata_phy.ctrl.need_reset)
 		self.sata_con = SATACON(self.sata_phy)
 
 		self.sata_bist = SATABIST(self.sata_con.crossbar.get_ports(2), with_control=True)

test/test_bist_mila.py

@@ -5,7 +5,8 @@ from bist import *
 from miscope.host.drivers import MiLaDriver
 
 mila = MiLaDriver(wb.regs, "mila")
-bist = SATABISTDriver(wb.regs)
+generator = SATABISTGeneratorDriver(wb.regs, "sata_bist")
+checker = SATABISTCheckerDriver(wb.regs, "sata_bist")
 wb.open()
 regs = wb.regs
 ###
@@ -27,8 +28,8 @@ mila.prog_sum("term")
 # Trigger / wait / receive
 mila.trigger(offset=32, length=1024)
 
-bist.write(0, 16, 1)
-bist.read(0, 16, 1)
+generator.run(0, 16, 1, 0)
+checker.run(0, 16, 1, 0)
 mila.wait_done()
 
 mila.read()