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adc: double-register asynchronous inputs

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This commit is contained in:
Sebastien Bourdeauducq 2013-04-19 12:32:12 +02:00
parent 0dca526a85
commit 117b3b8ec7
1 changed files with 6 additions and 3 deletions
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9
milkymist/adc/__init__.py
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@ -2,9 +2,10 @@ from migen.fhdl.structure import *
from migen.fhdl.module import Module from migen.fhdl.module import Module
from migen.bank.description import * from migen.bank.description import *
from migen.genlib.misc import optree from migen.genlib.misc import optree
from migen.genlib.cdc import MultiReg
class CounterADC(Module, AutoCSR): class CounterADC(Module, AutoCSR):
def __init__(self, charge, sense, width = 24): def __init__(self, charge, sense, width=24):
if not isinstance(sense, collections.Iterable): if not isinstance(sense, collections.Iterable):
sense = [sense] sense = [sense]
@ -36,7 +37,7 @@ class CounterADC(Module, AutoCSR):
count.eq(0), count.eq(0),
busy.eq((1 << channels)-1), busy.eq((1 << channels)-1),
self._overflow.status.eq(0), self._overflow.status.eq(0),
charge.eq(~self._polarity.storage) charge.eq(~self._polarity.storage)
).Elif(any_busy, ).Elif(any_busy,
Cat(count, carry).eq(count + 1), Cat(count, carry).eq(count + 1),
If(carry, If(carry,
@ -49,8 +50,10 @@ class CounterADC(Module, AutoCSR):
] ]
for i in range(channels): for i in range(channels):
sense_synced = Signal()
self.specials += MultiReg(sense[i], sense_synced)
self.sync += If(busy[i], self.sync += If(busy[i],
If(sense[i] != self._polarity.storage, If(sense_synced != self._polarity.storage,
res[i].status.eq(count), res[i].status.eq(count),
busy[i].eq(0) busy[i].eq(0)
) )