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soc/cores/cpu/urv: Fix add_sources.

This commit is contained in:
Florent Kermarrec 2024-11-05 17:33:32 +01:00
parent 20b0e98fe0
commit 1204cfda9d
1 changed files with 16 additions and 17 deletions
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33
litex/soc/cores/cpu/urv/core.py
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@ -201,24 +201,23 @@ class uRV(CPU):
def add_sources(platform, variant): def add_sources(platform, variant):
if not os.path.exists("urv-core"): if not os.path.exists("urv-core"):
os.system(f"git clone https://ohwr.org/project/urv-core/") os.system(f"git clone https://ohwr.org/project/urv-core/")
vdir = "urv-core/rtl"
platform.add_verilog_include_path("urv-core/rtl") platform.add_verilog_include_path("urv-core/rtl")
platform.add_sources([ platform.add_sources("urv-core/rtl",
"urv-core/rtl/urv_cpu.v", "urv_cpu.v",
"urv-core/rtl/urv_exec.v", "urv_exec.v",
"urv-core/rtl/urv_fetch.v", "urv_fetch.v",
"urv-core/rtl/urv_decode.v", "urv_decode.v",
"urv-core/rtl/urv_regfile.v", "urv_regfile.v",
"urv-core/rtl/urv_writeback.v", "urv_writeback.v",
"urv-core/rtl/urv_shifter.v", "urv_shifter.v",
"urv-core/rtl/urv_multiply.v", "urv_multiply.v",
"urv-core/rtl/urv_divide.v", "urv_divide.v",
"urv-core/rtl/urv_csr.v", "urv_csr.v",
"urv-core/rtl/urv_timer.v", "urv_timer.v",
"urv-core/rtl/urv_exceptions.v", "urv_exceptions.v",
"urv-core/rtl/urv_iram.v", "urv_iram.v",
"urv-core/rtl/urv_ecc.v", "urv_ecc.v",
]) )
def do_finalize(self): def do_finalize(self):
self.specials += Instance("urv_cpu", **self.cpu_params) self.specials += Instance("urv_cpu", **self.cpu_params)