Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

soc/cores/hyperbus: Cleanup parameters.

This commit is contained in:
Florent Kermarrec 2024-08-22 16:23:03 +02:00
parent b9210e7553
commit 120715a3d1
1 changed files with 15 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
litex/soc/cores/hyperbus.py
View File

@ -35,6 +35,9 @@ class HyperRAMPHY(LiteXModule):
# # # # # #
# Parameters.
# ----------
self.clk_domain = clk_domain
_sync = getattr(self.sync, clk_domain) _sync = getattr(self.sync, clk_domain)
# Rst. # Rst.
@ -140,18 +143,21 @@ class HyperRAM(LiteXModule):
# Parameters. # Parameters.
# ----------- # -----------
data_width = len(pads.dq) if not hasattr(pads.dq, "oe") else len(pads.dq.o) data_width = len(getattr(pads.dq, "o", pads.dq))
assert data_width in [8, 16] assert data_width in [8, 16]
assert latency_mode in ["fixed", "variable"] assert latency_mode in ["fixed", "variable"]
assert clk_ratio in [ assert clk_ratio in [
"4:1", # HyperRAM Clk = Sys Clk/4. "4:1", # HyperRAM Clk = Sys Clk/4.
"2:1", # HyperRAM Clk = Sys Clk/2. "2:1", # HyperRAM Clk = Sys Clk/2.
] ]
self.cd_io = cd_io = {
"4:1": "sys", # PHY.
"2:1": "sys2x" # ----
}[clk_ratio] self.phy = phy = HyperRAMPHY(
self.sync_io = sync_io = getattr(self.sync, cd_io) pads = pads,
data_width = data_width,
clk_domain = {"4:1": "sys", "2:1": "sys2x"}[clk_ratio],
)
# Config/Reg Interface. # Config/Reg Interface.
# --------------------- # ---------------------
@ -178,12 +184,7 @@ class HyperRAM(LiteXModule):
sr = Signal(48) sr = Signal(48)
sr_next = Signal(48) sr_next = Signal(48)
# PHY.
# ----
self.phy = phy = HyperRAMPHY(pads=pads, data_width=data_width, clk_domain=cd_io)
# Drive Control Signals -------------------------------------------------------------------- # Drive Control Signals --------------------------------------------------------------------
self.comb += [ self.comb += [
phy.rst.eq(self.conf_rst), phy.rst.eq(self.conf_rst),
phy.cs.eq(cs), phy.cs.eq(cs),
@ -439,7 +440,7 @@ class HyperRAM(LiteXModule):
self.status.fields.clk_ratio.eq({ self.status.fields.clk_ratio.eq({
"sys" : 4, "sys" : 4,
"sys2x": 2, "sys2x": 2,
}[self.cd_io]), }[self.phy.clk_domain]),
] ]
# Reg Interface. # Reg Interface.