build/xilinx/common: improve presentation
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60873a5b73
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124dff8f3f
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@ -93,10 +93,12 @@ class XilinxAsyncResetSynchronizerImpl(Module):
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self.comb += async_reset.eq(i)
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self.comb += async_reset.eq(i)
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rst_meta = Signal()
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rst_meta = Signal()
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self.specials += [
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self.specials += [
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Instance("FDPE", p_INIT=1, i_D=0, i_PRE=async_reset,
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Instance("FDPE",
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p_INIT=1, i_D=0, i_PRE=async_reset,
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i_CE=1, i_C=cd.clk, o_Q=rst_meta,
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i_CE=1, i_C=cd.clk, o_Q=rst_meta,
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attr={"async_reg", "ars_ff1"}),
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attr={"async_reg", "ars_ff1"}),
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Instance("FDPE", p_INIT=1, i_D=rst_meta, i_PRE=async_reset,
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Instance("FDPE", p_INIT=1,
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i_D=rst_meta, i_PRE=async_reset,
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i_CE=1, i_C=cd.clk, o_Q=cd.rst,
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i_CE=1, i_C=cd.clk, o_Q=cd.rst,
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attr={"async_reg", "ars_ff2"})
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attr={"async_reg", "ars_ff2"})
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]
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]
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