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build/xilinx/common: improve presentation

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This commit is contained in:
Florent Kermarrec 2019-08-08 16:08:55 +02:00
parent 60873a5b73
commit 124dff8f3f
1 changed files with 15 additions and 13 deletions
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6
litex/build/xilinx/common.py
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@ -93,10 +93,12 @@ class XilinxAsyncResetSynchronizerImpl(Module):
self.comb += async_reset.eq(i) self.comb += async_reset.eq(i)
rst_meta = Signal() rst_meta = Signal()
self.specials += [ self.specials += [
Instance("FDPE", p_INIT=1, i_D=0, i_PRE=async_reset, Instance("FDPE",
p_INIT=1, i_D=0, i_PRE=async_reset,
i_CE=1, i_C=cd.clk, o_Q=rst_meta, i_CE=1, i_C=cd.clk, o_Q=rst_meta,
attr={"async_reg", "ars_ff1"}), attr={"async_reg", "ars_ff1"}),
Instance("FDPE", p_INIT=1, i_D=rst_meta, i_PRE=async_reset, Instance("FDPE", p_INIT=1,
i_D=rst_meta, i_PRE=async_reset,
i_CE=1, i_C=cd.clk, o_Q=cd.rst, i_CE=1, i_C=cd.clk, o_Q=cd.rst,
attr={"async_reg", "ars_ff2"}) attr={"async_reg", "ars_ff2"})
] ]