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liteeth/example_designs: use new Keep SynthesisDirective

This commit is contained in:
Florent Kermarrec 2015-06-23 16:15:28 +02:00
parent 351e654e9d
commit 125432b5b6
1 changed files with 6 additions and 0 deletions
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6
misoclib/com/liteeth/example_designs/targets/base.py
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@ -1,6 +1,7 @@
from migen.bus import wishbone from migen.bus import wishbone
from migen.bank.description import * from migen.bank.description import *
from migen.genlib.io import CRG from migen.genlib.io import CRG
from migen.fhdl.specials import Keep
from mibuild.xilinx.vivado import XilinxVivadoToolchain from mibuild.xilinx.vivado import XilinxVivadoToolchain
from misoclib.soc import SoC from misoclib.soc import SoC
@ -45,6 +46,11 @@ class BaseSoC(SoC, AutoCSR):
self.submodules.core = LiteEthUDPIPCore(self.phy, mac_address, convert_ip(ip_address), clk_freq) self.submodules.core = LiteEthUDPIPCore(self.phy, mac_address, convert_ip(ip_address), clk_freq)
if isinstance(platform.toolchain, XilinxVivadoToolchain): if isinstance(platform.toolchain, XilinxVivadoToolchain):
self.specials += [
Keep(self.crg.cd_sys.clk),
Keep(self.phy.crg.cd_eth_rx.clk),
Keep(self.phy.crg.cd_eth_tx.clk)
]
platform.add_platform_command(""" platform.add_platform_command("""
create_clock -name sys_clk -period 6.0 [get_nets sys_clk] create_clock -name sys_clk -period 6.0 [get_nets sys_clk]
create_clock -name eth_rx_clk -period 8.0 [get_nets eth_rx_clk] create_clock -name eth_rx_clk -period 8.0 [get_nets eth_rx_clk]