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Update Nax/Vexii

This commit is contained in:
Dolu1990 2024-07-10 09:35:34 +02:00
parent 372ab25273
commit 1267ba8ae6
2 changed files with 7 additions and 2 deletions
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5
litex/soc/cores/cpu/naxriscv/core.py
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@ -322,7 +322,7 @@ class NaxRiscv(CPU):
ndir = os.path.join(vdir, "ext", "NaxRiscv") ndir = os.path.join(vdir, "ext", "NaxRiscv")
sdir = os.path.join(vdir, "ext", "SpinalHDL") sdir = os.path.join(vdir, "ext", "SpinalHDL")
NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git", "main", "f3357383", NaxRiscv.update_repo) NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git", "main", "43195dd1", NaxRiscv.update_repo)
gen_args = [] gen_args = []
gen_args.append(f"--netlist-name={NaxRiscv.netlist_name}") gen_args.append(f"--netlist-name={NaxRiscv.netlist_name}")
@ -368,6 +368,7 @@ class NaxRiscv(CPU):
# Add RAM. # Add RAM.
# By default, use Generic RAM implementation. # By default, use Generic RAM implementation.
ram_filename = "Ram_1w_1rs_Generic.v" ram_filename = "Ram_1w_1rs_Generic.v"
lutram_filename = "Ram_1w_1ra_Generic.v"
# On Altera/Intel platforms, use specific implementation. # On Altera/Intel platforms, use specific implementation.
from litex.build.altera import AlteraPlatform from litex.build.altera import AlteraPlatform
if isinstance(platform, AlteraPlatform): if isinstance(platform, AlteraPlatform):
@ -377,6 +378,8 @@ class NaxRiscv(CPU):
if isinstance(platform, EfinixPlatform): if isinstance(platform, EfinixPlatform):
ram_filename = "Ram_1w_1rs_Efinix.v" ram_filename = "Ram_1w_1rs_Efinix.v"
platform.add_source(os.path.join(vdir, ram_filename), "verilog") platform.add_source(os.path.join(vdir, ram_filename), "verilog")
platform.add_source(os.path.join(vdir, lutram_filename), "verilog")
# Add Cluster. # Add Cluster.
platform.add_source(os.path.join(vdir, self.netlist_name + ".v"), "verilog") platform.add_source(os.path.join(vdir, self.netlist_name + ".v"), "verilog")

4
litex/soc/cores/cpu/vexiiriscv/core.py
View File

@ -148,7 +148,7 @@ class VexiiRiscv(CPU):
vdir = get_data_mod("cpu", "vexiiriscv").data_location vdir = get_data_mod("cpu", "vexiiriscv").data_location
ndir = os.path.join(vdir, "ext", "VexiiRiscv") ndir = os.path.join(vdir, "ext", "VexiiRiscv")
NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "e991b315", args.update_repo) NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "ee92608a", args.update_repo)
if not args.cpu_variant: if not args.cpu_variant:
args.cpu_variant = "standard" args.cpu_variant = "standard"
@ -378,6 +378,7 @@ class VexiiRiscv(CPU):
# Add RAM. # Add RAM.
# By default, use Generic RAM implementation. # By default, use Generic RAM implementation.
ram_filename = "Ram_1w_1rs_Generic.v" ram_filename = "Ram_1w_1rs_Generic.v"
lutram_filename = "Ram_1w_1ra_Generic.v"
# On Altera/Intel platforms, use specific implementation. # On Altera/Intel platforms, use specific implementation.
from litex.build.altera import AlteraPlatform from litex.build.altera import AlteraPlatform
if isinstance(platform, AlteraPlatform): if isinstance(platform, AlteraPlatform):
@ -387,6 +388,7 @@ class VexiiRiscv(CPU):
if isinstance(platform, EfinixPlatform): if isinstance(platform, EfinixPlatform):
ram_filename = "Ram_1w_1rs_Efinix.v" ram_filename = "Ram_1w_1rs_Efinix.v"
platform.add_source(os.path.join(vdir, ram_filename), "verilog") platform.add_source(os.path.join(vdir, ram_filename), "verilog")
platform.add_source(os.path.join(vdir, lutram_filename), "verilog")
# Add Cluster. # Add Cluster.
platform.add_source(os.path.join(vdir, self.netlist_name + ".v"), "verilog") platform.add_source(os.path.join(vdir, self.netlist_name + ".v"), "verilog")