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soc_sdram: revert vivado l2 cache workaround (still seems to cause issues on some cases...)

This commit is contained in:
Florent Kermarrec 2018-09-07 11:51:17 +02:00
parent 2b786065b1
commit 12a8944711
1 changed files with 9 additions and 2 deletions
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11
litex/soc/integration/soc_sdram.py
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@ -72,8 +72,15 @@ class SoCSDRAM(SoCCore):
if self.l2_size: if self.l2_size:
port = self.sdram.crossbar.get_port() port = self.sdram.crossbar.get_port()
self.submodules.l2_cache = wishbone.Cache( l2_cache = wishbone.Cache(self.l2_size//4, self._wb_sdram, wishbone.Interface(port.dw))
self.l2_size//4, self._wb_sdram, wishbone.Interface(port.data_width)) # XXX Vivado ->2018.2 workaround, Vivado is not able to map correctly our L2 cache.
# Issue is reported to Xilinx, Remove this if ever fixed by Xilinx...
from litex.build.xilinx.vivado import XilinxVivadoToolchain
if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
from migen.fhdl.simplify import FullMemoryWE
self.submodules.l2_cache = FullMemoryWE()(l2_cache)
else:
self.submodules.l2_cache = l2_cache
self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(self.l2_cache.slave, port) self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(self.l2_cache.slave, port)
def do_finalize(self): def do_finalize(self):