cpu/fazyrv: Fix minor path typo

2024-03-04 21:44:18 +01:00 · 2024-03-04 21:44:18 +01:00 · 12b9c8b2e7
parent 044760e06c
commit 12b9c8b2e7
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/cores/cpu/fazyrv/core.py
+++ b/litex/soc/cores/cpu/fazyrv/core.py
@ -132,7 +132,7 @@ class FazyRV(CPU):

    @staticmethod
    def add_sources(platform, variant):
-        if not os.path.exists("FazyR"):
+        if not os.path.exists("FazyRV"):
            os.system(f"git clone https://github.com/meiniKi/FazyRV")
        vdir = "FazyRV/rtl"
        platform.add_verilog_include_path(vdir)