Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

integration/soc/add_ethernet: add phy_cd parameter to allow and demonstrate multiple PHYs support.

This commit is contained in:
Florent Kermarrec 2020-12-22 09:03:00 +01:00
parent c79135c573
commit 12dabde77c
1 changed files with 5 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
litex/soc/integration/soc.py
View File

@ -1327,17 +1327,20 @@ class LiteXSoC(SoC):
port = port, port = port,
base_address = self.bus.regions["main_ram"].origin) base_address = self.bus.regions["main_ram"].origin)
# Add Ethernet --------------------------------------------------------------------------------- # Add Ethernet ---------------------------------------------------------------------------------
def add_ethernet(self, name="ethmac", phy=None): def add_ethernet(self, name="ethmac", phy=None, phy_cd="eth"):
# Imports # Imports
from liteeth.mac import LiteEthMAC from liteeth.mac import LiteEthMAC
# MAC # MAC
ethmac = LiteEthMAC( ethmac = LiteEthMAC(
phy = phy, phy = phy,
dw = 32, dw = 32,
interface = "wishbone", interface = "wishbone",
endianness = self.cpu.endianness) endianness = self.cpu.endianness)
ethmac = ClockDomainsRenamer({
"eth_tx": phy_cd + "_tx",
"eth_rx": phy_cd + "_rx"})(ethmac)
setattr(self.submodules, name, ethmac) setattr(self.submodules, name, ethmac)
ethmac_region = SoCRegion(origin=self.mem_map.get(name, None), size=0x2000, cached=False) ethmac_region = SoCRegion(origin=self.mem_map.get(name, None), size=0x2000, cached=False)
self.bus.add_slave(name=name, slave=ethmac.bus, region=ethmac_region) self.bus.add_slave(name=name, slave=ethmac.bus, region=ethmac_region)