soc/SoCBusHandler: Integrate interconnect code since avoid duplication and simplify reuse.
Also extends supported data_widths.
A simple custom interconnect can now be created with code like this:
# Create 2 AXI Masters / 2 AXI Slaves.
axi_m_0 = axi.AXIInterface(data_width=32, address_width=32)
axi_m_1 = axi.AXIInterface(data_width=64, address_width=32)
axi_s_0 = axi.AXIInterface(data_width=512, address_width=32)
axi_s_1 = axi.AXIInterface(data_width=512, address_width=32)
axi_s_0_region = SoCRegion(origin=0x00000000, size=0x10000000)
axi_s_1_region = SoCRegion(origin=0x10000000, size=0x10000000)
# Create Bus Handler .
self.custom_bus = SoCBusHandler(
name = "SoCCustomBusHandler",
standard = "axi",
data_width = 512,
address_width = 32,
bursting = True,
interconnect = "crossbar",
interconnect_register = True,
)
# Add AXI Buses.
self.custom_bus.add_master(master=axi_m_0)
self.custom_bus.add_master(master=axi_m_1)
self.custom_bus.add_slave(slave=axi_s_0, region=axi_s_0_region)
self.custom_bus.add_slave(slave=axi_s_0, region=axi_s_1_region)
# Finalize.
self.custom_bus.finalize()
print(self.custom_bus)
This commit is contained in:
Florent Kermarrec
parent
3603e90ed8
commit
13448b8260
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@ -115,7 +115,7 @@ class SoCCSRRegion:
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class SoCBusHandler(LiteXModule):
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supported_standard = ["wishbone", "axi-lite", "axi"]
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supported_data_width = [32, 64]
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supported_data_width = [32, 64, 128, 256, 512]
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supported_address_width = [32]
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# Creation -------------------------------------------------------------------------------------
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@ -125,7 +125,7 @@ class SoCBusHandler(LiteXModule):
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address_width = 32,
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timeout = 1e6,
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bursting = False,
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interconnect = "shared",
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interconnect = "shared", interconnect_register=True,
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reserved_regions = {}
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):
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self.logger = logging.getLogger(name)
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@ -161,6 +161,7 @@ class SoCBusHandler(LiteXModule):
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self.address_width = address_width
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self.bursting = bursting
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self.interconnect = interconnect
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self.interconnect_register = interconnect_register
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self.masters = {}
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self.slaves = {}
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self.regions = {}
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@ -462,6 +463,48 @@ class SoCBusHandler(LiteXModule):
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# Else just return address_width:
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return self.address_width
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def do_finalize(self):
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interconnect_p2p_cls = {
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"wishbone": wishbone.InterconnectPointToPoint,
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"axi-lite": axi.AXILiteInterconnectPointToPoint,
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"axi" : axi.AXIInterconnectPointToPoint,
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}[self.standard]
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interconnect_shared_cls = {
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"wishbone": wishbone.InterconnectShared,
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"axi-lite": axi.AXILiteInterconnectShared,
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"axi" : axi.AXIInterconnectShared,
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}[self.standard]
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interconnect_crossbar_cls = {
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"wishbone": wishbone.Crossbar,
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"axi-lite": axi.AXILiteCrossbar,
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"axi" : axi.AXICrossbar,
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}[self.standard]
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if len(self.masters) and len(self.slaves):
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# If 1 bus_master, 1 bus_slave and no address translation, use InterconnectPointToPoint.
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if ((len(self.masters) == 1) and
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(len(self.slaves) == 1) and
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(next(iter(self.regions.values())).origin == 0)):
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self._interconnect = interconnect_p2p_cls(
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master = next(iter(self.masters.values())),
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slave = next(iter(self.slaves.values())))
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# Otherwise, use InterconnectShared/Crossbar.
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else:
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interconnect_cls = {
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"shared" : interconnect_shared_cls,
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"crossbar": interconnect_crossbar_cls,
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}[self.interconnect]
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self._interconnect = interconnect_cls(
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masters = list(self.masters.values()),
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slaves = [(self.regions[n].decoder(self), s) for n, s in self.slaves.items()],
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register = self.interconnect_register,
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timeout_cycles = self.timeout
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)
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self.logger.info("Interconnect: {} ({} <-> {}).".format(
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colorer(self._interconnect.__class__.__name__),
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colorer(len(self.masters)),
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colorer(len(self.slaves))))
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# Str ------------------------------------------------------------------------------------------
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def __str__(self):
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r = "{}-bit {} Bus, {}GiB Address Space.\n".format(
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@ -1121,48 +1164,10 @@ class SoC(LiteXModule):
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)
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# SoC Bus Interconnect ---------------------------------------------------------------------
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interconnect_p2p_cls = {
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"wishbone": wishbone.InterconnectPointToPoint,
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"axi-lite": axi.AXILiteInterconnectPointToPoint,
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"axi" : axi.AXIInterconnectPointToPoint,
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}[self.bus.standard]
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interconnect_shared_cls = {
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"wishbone": wishbone.InterconnectShared,
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"axi-lite": axi.AXILiteInterconnectShared,
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"axi" : axi.AXIInterconnectShared,
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}[self.bus.standard]
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interconnect_crossbar_cls = {
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"wishbone": wishbone.Crossbar,
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"axi-lite": axi.AXILiteCrossbar,
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"axi" : axi.AXICrossbar,
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}[self.bus.standard]
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if len(self.bus.masters) and len(self.bus.slaves):
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# If 1 bus_master, 1 bus_slave and no address translation, use InterconnectPointToPoint.
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if ((len(self.bus.masters) == 1) and
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(len(self.bus.slaves) == 1) and
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(next(iter(self.bus.regions.values())).origin == 0)):
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self.bus_interconnect = interconnect_p2p_cls(
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master = next(iter(self.bus.masters.values())),
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slave = next(iter(self.bus.slaves.values())))
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# Otherwise, use InterconnectShared/Crossbar.
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else:
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interconnect_cls = {
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"shared" : interconnect_shared_cls,
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"crossbar": interconnect_crossbar_cls,
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}[self.bus.interconnect]
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self.bus_interconnect = interconnect_cls(
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masters = list(self.bus.masters.values()),
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slaves = [(self.bus.regions[n].decoder(self.bus), s) for n, s in self.bus.slaves.items()],
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register = True,
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timeout_cycles = self.bus.timeout)
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self.bus.finalize()
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if hasattr(self, "ctrl") and self.bus.timeout is not None:
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if hasattr(self.ctrl, "bus_error") and hasattr(self.bus_interconnect, "timeout"):
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self.comb += self.ctrl.bus_error.eq(self.bus_interconnect.timeout.error)
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self.bus.logger.info("Interconnect: {} ({} <-> {}).".format(
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colorer(self.bus_interconnect.__class__.__name__),
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colorer(len(self.bus.masters)),
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colorer(len(self.bus.slaves))))
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if hasattr(self.ctrl, "bus_error") and hasattr(self.bus._interconnect, "timeout"):
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self.comb += self.ctrl.bus_error.eq(self.bus._interconnect.timeout.error)
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self.add_config("BUS_STANDARD", self.bus.standard.upper())
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self.add_config("BUS_DATA_WIDTH", self.bus.data_width)
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self.add_config("BUS_ADDRESS_WIDTH", self.bus.address_width)
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@ -1170,24 +1175,7 @@ class SoC(LiteXModule):
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# SoC DMA Bus Interconnect (Cache Coherence) -----------------------------------------------
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if hasattr(self, "dma_bus"):
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if len(self.dma_bus.masters) and len(self.dma_bus.slaves):
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# If 1 bus_master, 1 bus_slave and no address translation, use InterconnectPointToPoint.
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if ((len(self.dma_bus.masters) == 1) and
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(len(self.dma_bus.slaves) == 1) and
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(next(iter(self.dma_bus.regions.values())).origin == 0)):
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self.dma_bus_interconnect = wishbone.InterconnectPointToPoint(
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master = next(iter(self.dma_bus.masters.values())),
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slave = next(iter(self.dma_bus.slaves.values())))
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# Otherwise, use InterconnectShared.
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else:
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self.dma_bus_interconnect = wishbone.InterconnectShared(
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masters = list(self.dma_bus.masters.values()),
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slaves = [(self.dma_bus.regions[n].decoder(self.dma_bus), s) for n, s in self.dma_bus.slaves.items()],
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register = True)
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self.bus.logger.info("DMA Interconnect: {} ({} <-> {}).".format(
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colorer(self.dma_bus_interconnect.__class__.__name__),
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colorer(len(self.dma_bus.masters)),
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colorer(len(self.dma_bus.slaves))))
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self.dma_bus.finalize()
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self.add_config("CPU_HAS_DMA_BUS")
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# SoC Main CSRs collection -----------------------------------------------------------------
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