cores/spi_flash: Minor cosmetic cleanups, SpiFlashQuadReadWrite has also been moved to the end with a Note since should probably be re-factored.
This commit is contained in:
Florent Kermarrec
parent
61dcd1e8fd
commit
134c628357
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@ -61,20 +61,22 @@ class SpiFlashCommon(Module):
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# Xilinx 7-series
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if device[:3] == "xc7":
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self.specials += Instance("STARTUPE2",
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i_CLK=0,
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i_GSR=0,
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i_GTS=0,
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i_KEYCLEARB=0,
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i_PACK=0,
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i_USRCCLKO=self.pads.clk,
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i_USRCCLKTS=0,
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i_USRDONEO=1,
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i_USRDONETS=1)
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i_CLK = 0,
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i_GSR = 0,
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i_GTS = 0,
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i_KEYCLEARB = 0,
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i_PACK = 0,
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i_USRCCLKO = self.pads.clk,
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i_USRCCLKTS = 0,
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i_USRDONEO = 1,
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i_USRDONETS = 1
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)
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# Lattice ECP5
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elif device[:4] == "LFE5":
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self.specials += Instance("USRMCLK",
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i_USRMCLKI=self.pads.clk,
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i_USRMCLKTS=0)
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i_USRMCLKI = self.pads.clk,
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i_USRMCLKTS = 0
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)
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else:
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raise NotImplementedError
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self.clk_primitive_registered = True
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@ -83,6 +85,7 @@ class SpiFlashCommon(Module):
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if hasattr(self, "clk_primitive_needed"):
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assert self.clk_primitive_registered == True
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class SpiFlashDualQuad(SpiFlashCommon, AutoCSR):
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def __init__(self, pads, dummy=15, div=2, with_bitbang=True, endianness="big"):
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"""
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@ -98,9 +101,9 @@ class SpiFlashDualQuad(SpiFlashCommon, AutoCSR):
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if with_bitbang:
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self.bitbang = CSRStorage(4, reset_less=True, fields=[
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CSRField("mosi", description="Output value for MOSI pin, valid whenever ``dir`` is ``0``."),
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CSRField("clk", description="Output value for SPI CLK pin."),
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CSRField("clk", description="Output value for SPI CLK pin."),
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CSRField("cs_n", description="Output value for SPI CSn pin."),
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CSRField("dir", description="Sets the direction for *ALL* SPI data pins except CLK and CSn.", values=[
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CSRField("dir", description="Sets the direction for *ALL* SPI data pins except CLK and CSn.", values=[
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("0", "OUT", "SPI pins are all output"),
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("1", "IN", "SPI pins are all input"),
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])
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@ -114,12 +117,11 @@ class SpiFlashDualQuad(SpiFlashCommon, AutoCSR):
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# # #
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cs_n = Signal(reset=1)
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clk = Signal()
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cs_n = Signal(reset=1)
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clk = Signal()
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dq_oe = Signal()
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wbone_width = len(bus.dat_r)
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read_cmd_params = {
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4: (_format_cmd(_QIOFR, 4), 4*8),
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2: (_format_cmd(_DIOFR, 2), 2*8),
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@ -228,6 +230,7 @@ class SpiFlashDualQuad(SpiFlashCommon, AutoCSR):
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self.sync += timeline(bus.cyc & bus.stb & (i == div - 1), tseq)
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class SpiFlashSingle(SpiFlashCommon, AutoCSR):
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def __init__(self, pads, dummy=15, div=2, with_bitbang=True, endianness="big"):
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"""
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@ -240,9 +243,9 @@ class SpiFlashSingle(SpiFlashCommon, AutoCSR):
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if with_bitbang:
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self.bitbang = CSRStorage(4, reset_less=True, fields=[
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CSRField("mosi", description="Output value for SPI MOSI pin."),
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CSRField("clk", description="Output value for SPI CLK pin."),
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CSRField("clk", description="Output value for SPI CLK pin."),
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CSRField("cs_n", description="Output value for SPI CSn pin."),
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CSRField("dir", description="Unused in this design.")
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CSRField("dir", description="Unused in this design.")
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], description="""Bitbang controls for SPI output.""")
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self.miso = CSRStatus(description="Incoming value of MISO pin.")
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self.bitbang_en = CSRStorage(description="Write a ``1`` here to disable memory-mapped mode and enable bitbang mode.")
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@ -256,7 +259,7 @@ class SpiFlashSingle(SpiFlashCommon, AutoCSR):
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self.comb += pads.hold.eq(1)
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cs_n = Signal(reset=1)
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clk = Signal()
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clk = Signal()
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wbone_width = len(bus.dat_r)
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read_cmd = _FAST_READ
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@ -348,8 +351,59 @@ def SpiFlash(pads, *args, **kwargs):
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else:
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return SpiFlashDualQuad(pads, *args, **kwargs)
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# Xilinx 7-Series FPGAs SPI Flash (non-memory-mapped) ----------------------------------------------
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class S7SPIFlash(Module, AutoCSR):
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def __init__(self, pads, sys_clk_freq, spi_clk_freq=25e6):
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self.submodules.spi = spi = SPIMaster(None, 40, sys_clk_freq, spi_clk_freq)
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self.specials += Instance("STARTUPE2",
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i_CLK = 0,
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i_GSR = 0,
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i_GTS = 0,
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i_KEYCLEARB = 0,
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i_PACK = 0,
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i_USRCCLKO = spi.pads.clk,
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i_USRCCLKTS = 0,
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i_USRDONEO = 1,
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i_USRDONETS = 1
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)
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if hasattr(pads, "vpp"):
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pads.vpp.reset = 1
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if hasattr(pads, "hold"):
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pads.hold.reset = 1
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if hasattr(pads, "cs_n"):
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self.comb += pads.cs_n.eq(spi.pads.cs_n)
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self.comb += [
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pads.mosi.eq(spi.pads.mosi),
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spi.pads.miso.eq(pads.miso)
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]
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# Lattice ECP5 FPGAs SPI Flash (non-memory-mapped) -------------------------------------------------
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class ECP5SPIFlash(Module, AutoCSR):
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def __init__(self, pads, sys_clk_freq, spi_clk_freq=25e6):
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self.submodules.spi = spi = SPIMaster(None, 40, sys_clk_freq, spi_clk_freq)
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self.specials += Instance("USRMCLK",
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i_USRMCLKI = spi.pads.clk,
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i_USRMCLKTS = 0
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)
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if hasattr(pads, "vpp"):
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pads.vpp.reset = 1
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if hasattr(pads, "hold"):
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pads.hold.reset = 1
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if hasattr(pads, "cs_n"):
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self.comb += pads.cs_n.eq(spi.pads.cs_n)
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self.comb += [
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pads.mosi.eq(spi.pads.mosi),
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spi.pads.miso.eq(pads.miso)
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]
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# SpiFlash Quad Read/Write (memory-mapped) ---------------------------------------------------------
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# Note: This code too complicated and should probably be re-factored.
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class SpiFlashQuadReadWrite(SpiFlashCommon, AutoCSR):
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def __init__(self, pads, dummy=15, div=2, with_bitbang=True, endianness="big"):
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"""
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@ -579,51 +633,3 @@ class SpiFlashQuadReadWrite(SpiFlashCommon, AutoCSR):
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self.sync += timeline(queue.status[0] & ~self.en_quad.storage[0] & (i == div - 1), accumulate_timeline_deltas(read_seq))
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self.sync += timeline(queue.status[1] & ~self.en_quad.storage[0] & (i == div - 1), accumulate_timeline_deltas(write_seq))
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# Xilinx 7-Series FPGAs SPI Flash (non-memory-mapped) ----------------------------------------------
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class S7SPIFlash(Module, AutoCSR):
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def __init__(self, pads, sys_clk_freq, spi_clk_freq=25e6):
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self.submodules.spi = spi = SPIMaster(None, 40, sys_clk_freq, spi_clk_freq)
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self.specials += Instance("STARTUPE2",
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i_CLK=0,
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i_GSR=0,
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i_GTS=0,
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i_KEYCLEARB=0,
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i_PACK=0,
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i_USRCCLKO=spi.pads.clk,
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i_USRCCLKTS=0,
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i_USRDONEO=1,
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i_USRDONETS=1
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)
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if hasattr(pads, "vpp"):
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pads.vpp.reset = 1
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if hasattr(pads, "hold"):
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pads.hold.reset = 1
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if hasattr(pads, "cs_n"):
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self.comb += pads.cs_n.eq(spi.pads.cs_n)
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self.comb += [
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pads.mosi.eq(spi.pads.mosi),
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spi.pads.miso.eq(pads.miso)
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]
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# Lattice ECP5 FPGAs SPI Flash (non-memory-mapped) -------------------------------------------------
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class ECP5SPIFlash(Module, AutoCSR):
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def __init__(self, pads, sys_clk_freq, spi_clk_freq=25e6):
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self.submodules.spi = spi = SPIMaster(None, 40, sys_clk_freq, spi_clk_freq)
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self.specials += Instance("USRMCLK",
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i_USRMCLKI = spi.pads.clk,
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i_USRMCLKTS = 0
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)
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if hasattr(pads, "vpp"):
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pads.vpp.reset = 1
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if hasattr(pads, "hold"):
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pads.hold.reset = 1
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if hasattr(pads, "cs_n"):
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self.comb += pads.cs_n.eq(spi.pads.cs_n)
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self.comb += [
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pads.mosi.eq(spi.pads.mosi),
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spi.pads.miso.eq(pads.miso)
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]
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