bank: support raw registers

migen/bank/csrgen.py

@@ -22,14 +22,20 @@ class Bank:
 		bwcases = []
 		for i in range(nregs):
 			reg = self.description[i]
-			nfields = len(reg.fields)
+			if reg.raw is None:
 				bwra = [Constant(i, BV(nbits))]
+				nfields = len(reg.fields)
 				for j in range(nfields):
 					field = reg.fields[j]
 					if field.access_bus == WRITE_ONLY or field.access_bus == READ_WRITE:
 						bwra.append(field.storage.eq(self.interface.d_i[j]))
 				if len(bwra) > 1:
 					bwcases.append(bwra)
+			else:
+				comb.append(reg.dev_r.eq(self.interface.d_i[:reg.raw.width]))
+				comb.append(reg.dev_re.eq(self._sel & \
+					self.interface.we_i & \
+					(self.interface.a_i[:nbits] == Constant(i, BV(nbits)))))
 		if bwcases:
 			sync.append(If(self._sel & self.interface.we_i, Case(self.interface.a_i[:nbits], *bwcases)))
 		
@@ -37,6 +43,7 @@ class Bank:
 		brcases = []
 		for i in range(nregs):
 			reg = self.description[i]
+			if reg.raw is None:
 				nfields = len(reg.fields)
 				brs = []
 				reg_readable = False
@@ -52,6 +59,8 @@ class Bank:
 						brcases.append([Constant(i, BV(nbits)), self.interface.d_o.eq(f.Cat(*brs))])
 					else:
 						brcases.append([Constant(i, BV(nbits)), self.interface.d_o.eq(brs[0])])
+			else:
+				brcases.append([Constant(i, BV(nbits)), self.interface.d_o.eq(reg.dev_w)])
 		if brcases:
 			sync.append(self.interface.d_o.eq(Constant(0, BV(8))))
 			sync.append(If(self._sel, Case(self.interface.a_i[:nbits], *brcases)))
@@ -60,6 +69,7 @@ class Bank:
 		
 		# Device access
 		for reg in self.description:
+			if reg.raw is None:
 				for field in reg.fields:
 					if field.access_dev == READ_ONLY or field.access_dev == READ_WRITE:
 						comb.append(field.dev_r.eq(field.storage))

migen/bank/description.py

@@ -1,8 +1,14 @@
 from migen.fhdl.structure import *
 
 class Register:
-	def __init__(self, name):
+	def __init__(self, name, raw=None):
 		self.name = name
+		self.raw = raw
+		if raw is not None:
+			self.dev_re = Signal(name=name + "_re")
+			self.dev_r = Signal(raw, name + "_r")
+			self.dev_w = Signal(raw, name + "_w")
+		else:
 			self.fields = []
 	
 	def add_field(self, f):