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fhdl/verilog: fix representation of negative integers

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Give the explicit two's complement representation for the given bit width.

This results in less readable code compared to using unary minus,
but fixes a bug when trying to represent the most negative integer.
This commit is contained in:
Sebastien Bourdeauducq 2013-12-11 22:26:10 +01:00
parent d6cb981c7a
commit 135a4fea25
1 changed files with 2 additions and 1 deletions
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3
migen/fhdl/verilog.py
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@ -27,7 +27,8 @@ def _printintbool(node):
if node >= 0: if node >= 0:
return str(bits_for(node)) + "'d" + str(node), False return str(bits_for(node)) + "'d" + str(node), False
else: else:
return "-" + str(bits_for(node)) + "'sd" + str(-node), True nbits = bits_for(node)
return str(nbits) + "'sd" + str(2**nbits + node), True
else: else:
raise TypeError raise TypeError