test_i2c: update to use improved _MockTristate
* test now checks the actual i2c bus state, not the I2CMaster output * refactor to eliminate some copy/paste * tests now work again with this change: 'only change SDA when SCL is stable'
This commit is contained in:
Andrew Dennison
parent
b779933a5f
commit
13811aeacb
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@ -79,16 +79,19 @@ class TestI2C(unittest.TestCase):
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dut = I2CMaster(pads)
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def check_trans(scl, sda):
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scl_init, sda_init = (yield dut.i2c.scl_o), (yield dut.i2c.sda_o)
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scl, sda = int(scl), int(sda)
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scl_init, sda_init = (yield dut.scl_t.i), (yield dut.sda_t.i)
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timeout = 0
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while True:
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timeout += 1
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self.assertLess(timeout, 20)
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scl_now, sda_now = (yield dut.i2c.scl_o), (yield dut.i2c.sda_o)
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if scl_now != scl_init or sda_now != sda_init:
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self.assertEqual(scl_now, scl)
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self.assertEqual(sda_now, sda)
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scl_now, sda_now = (yield dut.scl_t.i), (yield dut.sda_t.i)
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if scl_now == scl and sda_now == sda:
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return
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timeout += 1
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self.assertLess(timeout, 20,
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"\n*** timeout waiting for: " +
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f"scl:{scl_now} checking:{scl_init}=>{scl} " +
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f"sda:{sda_now} checking:{sda_init}=>{sda} ***"
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)
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yield
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def wait_idle(do=lambda: ()):
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@ -102,28 +105,56 @@ class TestI2C(unittest.TestCase):
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yield
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def write_bit(value):
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#print(f"write_bit:{value}")
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yield from check_trans(scl=False, sda=value)
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yield from check_trans(scl=True, sda=value)
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def write_ack(value):
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#print(f"write_ack:{value}")
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yield from check_trans(scl=False, sda=not value)
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yield from check_trans(scl=True, sda=not value)
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yield from wait_idle()
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def read_bit(value):
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yield from check_trans(scl=False, sda=True)
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yield dut.sda_t.i.eq(value)
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yield from check_trans(scl=True, sda=True)
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#print(f"read_bit:{value}")
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yield from check_trans(scl=False, sda=(yield dut.sda_tristate.i_mock))
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yield dut.sda_tristate.i_mock.eq(value)
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yield from check_trans(scl=True, sda=value)
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# need to restore i_mock elsewhere
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def read_ack(value):
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#print(f"read_ack:{value}")
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yield from check_trans(scl=False, sda=True)
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yield dut.sda_t.i.eq(not value)
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yield from check_trans(scl=True, sda=True)
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yield dut.sda_tristate.i_mock.eq(not value)
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yield from check_trans(scl=True, sda=not value)
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yield from wait_idle()
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yield dut.sda_tristate.i_mock.eq(True)
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ack = ((yield from dut.bus.read(I2C_XFER_ADDR)) & I2C_ACK) != 0
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self.assertEqual(ack, value)
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def i2c_write(value, ack=True):
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value = int(value)
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test_bin = '{0:08b}'.format(value)
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#print(f"I2C_WRITE | {hex(value)}:0x{test_bin}")
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yield from dut.bus.write(I2C_XFER_ADDR, I2C_WRITE | value)
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for i in list(test_bin):
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yield from write_bit(int(i))
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yield from read_ack(True)
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def i2c_read(value, ack=True):
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value = int(value)
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test_bin = '{0:08b}'.format(value)
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#print(f"I2C_READ | {hex(value)}:0x{test_bin}")
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yield from dut.bus.write(I2C_XFER_ADDR, I2C_READ | (I2C_ACK if ack else 0))
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for i in list(test_bin):
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yield from read_bit(int(i))
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yield dut.sda_tristate.i_mock.eq(True)
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data = (yield from dut.bus.read(I2C_XFER_ADDR)) & 0xff
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self.assertEqual(data, value)
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yield from write_ack(ack)
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def check():
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yield from dut.bus.write(I2C_CONFIG_ADDR, 4)
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data = (yield from dut.bus.read(I2C_CONFIG_ADDR)) & 0xff
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self.assertEqual(data, 4)
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@ -132,39 +163,30 @@ class TestI2C(unittest.TestCase):
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yield from check_trans(scl=True, sda=False)
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yield from wait_idle()
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yield from dut.bus.write(I2C_XFER_ADDR, I2C_WRITE | 0x82)
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for i in [True, False, False, False, False, False, True, False]:
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yield from write_bit(i)
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yield from read_ack(True)
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yield from dut.bus.write(I2C_XFER_ADDR, I2C_WRITE | 0x18)
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for i in [False, False, False, True, True, False, False, False]:
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yield from write_bit(i)
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yield from read_ack(False)
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yield from i2c_write(0x82)
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yield from i2c_write(0x18, ack=False)
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yield from dut.bus.write(I2C_XFER_ADDR, I2C_START | I2C_STOP)
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yield from check_trans(scl=True, sda=False)
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yield from wait_idle()
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yield from dut.bus.write(I2C_XFER_ADDR, I2C_READ)
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for i in [False, False, False, True, True, False, False, False]:
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yield from read_bit(i)
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data = (yield from dut.bus.read(I2C_XFER_ADDR)) & 0xff
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self.assertEqual(data, 0x18)
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yield from write_ack(False)
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yield from dut.bus.write(I2C_XFER_ADDR, I2C_READ | I2C_ACK)
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for i in [True, False, False, False, True, False, False, False]:
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yield from read_bit(i)
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data = (yield dut.i2c.data)
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self.assertEqual(data, 0x88)
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yield from write_ack(True)
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yield from i2c_read(0x18, ack=False)
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yield from i2c_read(0x88)
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yield from dut.bus.write(I2C_XFER_ADDR, I2C_STOP)
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yield from check_trans(scl=False, sda=False)
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yield from wait_idle()
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run_simulation(dut, check(), special_overrides={Tristate: _MockTristate}, vcd_name="i2c.vcd")
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clocks = {
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"sys": 10,
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"async": (10, 3),
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}
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generators = {
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"sys": [
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check(),
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],
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}
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run_simulation(dut, generators, clocks, special_overrides={Tristate: _MockTristate}, vcd_name="i2c.vcd")
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if __name__ == "__main__":
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unittest.main()
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