Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

soc/add_cpu: Fix/Simplify CFU integration.

This commit is contained in:
Florent Kermarrec 2021-05-17 12:04:37 +02:00
parent d0e8de077c
commit 13979a43b7
2 changed files with 7 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
litex/soc/cores/cpu/vexriscv/core.py
View File

@ -121,7 +121,7 @@ class VexRiscv(CPU, AutoCSR):
flags += " -D__vexriscv__" flags += " -D__vexriscv__"
return flags return flags
def __init__(self, platform, variant="standard", with_timer=False, cfu=None): def __init__(self, platform, variant="standard", with_timer=False):
self.platform = platform self.platform = platform
self.variant = variant self.variant = variant
self.human_name = CPU_VARIANTS.get(variant, "VexRiscv") self.human_name = CPU_VARIANTS.get(variant, "VexRiscv")
@ -174,9 +174,6 @@ class VexRiscv(CPU, AutoCSR):
if "debug" in variant: if "debug" in variant:
self.add_debug() self.add_debug()
if "cfu" in variant:
self.add_cfu(cfu_filename="Cfu.v" if cfu is None else cfu)
def set_reset_address(self, reset_address): def set_reset_address(self, reset_address):
assert not hasattr(self, "reset_address") assert not hasattr(self, "reset_address")
self.reset_address = reset_address self.reset_address = reset_address

8
litex/soc/integration/soc.py
View File

@ -864,7 +864,7 @@ class SoC(Module):
self.add_config("CSR_DATA_WIDTH", self.csr.data_width) self.add_config("CSR_DATA_WIDTH", self.csr.data_width)
self.add_config("CSR_ALIGNMENT", self.csr.alignment) self.add_config("CSR_ALIGNMENT", self.csr.alignment)
def add_cpu(self, name="vexriscv", variant="standard", cls=None, reset_address=None, **kwargs): def add_cpu(self, name="vexriscv", variant="standard", cls=None, reset_address=None, cfu=None):
# Check that CPU is supported. # Check that CPU is supported.
if name not in cpu.CPUS.keys(): if name not in cpu.CPUS.keys():
self.logger.error("{} CPU {}, supporteds: {}.".format( self.logger.error("{} CPU {}, supporteds: {}.".format(
@ -887,7 +887,11 @@ class SoC(Module):
colorer(", ".join(cpu_cls.variants)))) colorer(", ".join(cpu_cls.variants))))
raise raise
self.check_if_exists("cpu") self.check_if_exists("cpu")
self.submodules.cpu = cpu_cls(self.platform, variant, **kwargs) self.submodules.cpu = cpu_cls(self.platform, variant)
# Add optional CFU plugin.
if "cfu" in variant and hasattr(self.cpu, "add_cfu"):
self.cpu.add_cfu(cfu_filename=cfu)
# Update SoC with CPU constraints. # Update SoC with CPU constraints.
for n, (origin, size) in enumerate(self.cpu.io_regions.items()): for n, (origin, size) in enumerate(self.cpu.io_regions.items()):