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soc/interconnect/axi/axi_lite: AXILiteInterconnectShared, AXILiteCrossbar: propagate master bus address width to Interface

This commit is contained in:
Gwenhael Goavec-Merou 2023-12-08 11:59:33 +01:00
parent 01ce8ab0d1
commit 13987659a9
1 changed files with 10 additions and 7 deletions
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7
litex/soc/interconnect/axi/axi_lite.py
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@ -137,6 +137,7 @@ def axi_lite_to_simple(axi_lite, port_adr, port_dat_r, port_dat_w=None, port_we=
do_read = Signal()
do_write = Signal()
last_was_read = Signal()
port_dat_r_latched = Signal(axi_lite.data_width)
comb = []
@ -777,7 +778,8 @@ class AXILiteInterconnectShared(LiteXModule):
"""AXI Lite shared interconnect"""
def __init__(self, masters, slaves, register=False, timeout_cycles=1e6):
data_width = get_check_parameters(ports=masters + [s for _, s in slaves])
shared = AXILiteInterface(data_width=data_width)
adr_width = max([m.address_width for m in masters])
shared = AXILiteInterface(data_width=data_width, address_width=adr_width)
self.arbiter = AXILiteArbiter(masters, shared)
self.decoder = AXILiteDecoder(shared, slaves)
if timeout_cycles is not None:
@ -790,8 +792,9 @@ class AXILiteCrossbar(LiteXModule):
"""
def __init__(self, masters, slaves, register=False, timeout_cycles=1e6):
data_width = get_check_parameters(ports=masters + [s for _, s in slaves])
adr_width = max([m.address_width for m in masters])
matches, busses = zip(*slaves)
access_m_s = [[AXILiteInterface(data_width=data_width) for j in slaves] for i in masters] # a[master][slave]
access_m_s = [[AXILiteInterface(data_width=data_width, address_width=adr_width) for j in slaves] for i in masters] # a[master][slave]
access_s_m = list(zip(*access_m_s)) # a[slave][master]
# Decode each master into its access row.
for slaves, master in zip(access_m_s, masters):