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soc/interconnect/axi: Add AXILite Clock Domain Crossing module.

This commit is contained in:
Florent Kermarrec 2021-03-15 10:18:12 +01:00
parent 11f7416e36
commit 13e13a094c
1 changed files with 42 additions and 1 deletions
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43
litex/soc/interconnect/axi.py
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@ -359,7 +359,6 @@ class AXIBurst2Beat(Module):
)
]
# AXI to AXI Lite ----------------------------------------------------------------------------------
class AXI2AXILite(Module):
@ -1083,6 +1082,48 @@ class AXILiteConverter(Module):
else:
self.comb += master.connect(slave)
# AXILite Clock Domain Crossing --------------------------------------------------------------------
class AXILiteClockDomainCrossing(Module):
"""AXILite Clock Domain Crossing"""
def __init__(self, master, slave, cd_from="sys", cd_to="sys"):
# Same Clock Domain, direct connection.
if cd_from == cd_to:
self.comb += [
# Write.
master.aw.connect(slave.aw),
master.w.connect(slave.w),
slave.b.connect(master.b),
# Read.
master.ar.connect(slave.ar),
slave.r.connect(master.r),
]
# Clock Domain Crossing.
else:
# Write.
aw_cdc = stream.ClockDomainCrossing(master.aw.description, cd_from, cd_to)
w_cdc = stream.ClockDomainCrossing(master.w.description, cd_from, cd_to)
b_cdc = stream.ClockDomainCrossing(master.b.description, cd_to, cd_from)
self.submodules += aw_cdc, w_cdc, b_cdc
self.comb += [
master.aw.connect(aw_cdc.sink),
aw_cdc.source.connect(slave.aw),
master.w.connect(w_cdc.sink),
w_cdc.source.connect(slave.w),
slave.b.connect(b_cdc.sink),
b_cdc.source.connect(master.b),
]
# Read.
ar_cdc = stream.ClockDomainCrossing(master.ar.description, cd_from, cd_to)
r_cdc = stream.ClockDomainCrossing(master.r.description, cd_to, cd_from)
self.submodules += ar_cdc, r_cdc
self.comb += [
master.ar.connect(ar_cdc.sink),
ar_cdc.source.connect(slave.ar),
slave.r.connect(r_cdc.sink),
r_cdc.source.connect(master.r),
]
# AXILite Timeout ----------------------------------------------------------------------------------
class AXILiteTimeout(Module):