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cpu/NaxRiscv update nax with peripheral memory region

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Dolu1990 2022-09-09 11:23:24 +02:00
parent a04f20880f
commit 14160ce7e3
1 changed files with 1 additions and 1 deletions
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litex/soc/cores/cpu/naxriscv/core.py
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@ -228,7 +228,7 @@ class NaxRiscv(CPU):
ndir = os.path.join(vdir, "ext", "NaxRiscv")
sdir = os.path.join(vdir, "ext", "SpinalHDL")
NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git" , "main", "7c61b64")
NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git" , "main", "cb2a598a")
NaxRiscv.git_setup("SpinalHDL", sdir, "https://github.com/SpinalHDL/SpinalHDL.git", "dev" , "a130f7b7")
gen_args = []