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wishbone2csr: refactor using FSM, reduce latency (make it asynchronous) and set csr.adr only when access is done (allow use of CSR/CSRBase we signal) 

Making it asynchronous does not seem to deteriorate timing or resource usage, if it's the case for some designs, we'll add a register parameter.
This commit is contained in:
Florent Kermarrec 2019-09-24 17:55:29 +02:00
parent ffd2be2ba0
commit 1425a68d9e
1 changed files with 17 additions and 10 deletions
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27
litex/soc/interconnect/wishbone2csr.py
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@ -1,5 +1,5 @@
# This file is Copyright (c) 2015 Sebastien Bourdeauducq <sb@m-labs.hk> # This file is Copyright (c) 2015 Sebastien Bourdeauducq <sb@m-labs.hk>
# This file is Copyright (c) 2015-2018 Florent Kermarrec <florent@enjoy-digital.fr> # This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD # License: BSD
from migen import * from migen import *
@ -17,16 +17,23 @@ class WB2CSR(Module):
bus_csr = csr_bus.Interface() bus_csr = csr_bus.Interface()
self.csr = bus_csr self.csr = bus_csr
### # # #
self.sync += [ self.comb += [
self.csr.we.eq(0),
self.csr.dat_w.eq(self.wishbone.dat_w), self.csr.dat_w.eq(self.wishbone.dat_w),
self.csr.adr.eq(self.wishbone.adr),
self.wishbone.dat_r.eq(self.csr.dat_r) self.wishbone.dat_r.eq(self.csr.dat_r)
] ]
self.sync += timeline(self.wishbone.cyc & self.wishbone.stb, [
(1, [self.csr.we.eq(self.wishbone.we)]), fsm = FSM(reset_state="WRITE-READ")
(2, [self.wishbone.ack.eq(1)]), self.submodules += fsm
(3, [self.wishbone.ack.eq(0)]) fsm.act("WRITE-READ",
]) If(self.wishbone.cyc & self.wishbone.stb,
self.csr.adr.eq(self.wishbone.adr),
self.csr.we.eq(self.wishbone.we),
NextState("ACK")
)
)
fsm.act("ACK",
self.wishbone.ack.eq(1),
NextState("WRITE-READ")
)