asmicon/multiplexer: correct read-to-write delay to prevent conflicts on the tag bus
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@ -239,7 +239,7 @@ class Multiplexer:
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# Control FSM
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fsm = FSM("READ", "WRITE", "REFRESH", delayed_enters=[
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("RTW", "WRITE", math.ceil((self.timing_settings.CL+1)/2)),
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("RTW", "WRITE", self.timing_settings.rd_delay),
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("WTR", "READ", self.timing_settings.tWR)
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])
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fsm.act(fsm.READ,
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