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soc/cores/clock: add Max10PLL.

This commit is contained in:
Florent Kermarrec 2020-04-08 08:54:12 +02:00
parent 2470ef5096
commit 14bf8b8190
1 changed files with 20 additions and 0 deletions
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20
litex/soc/cores/clock.py
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@ -884,3 +884,23 @@ class Cyclone10LPPLL(IntelClocking):
"-A7" : (0e6, 450e6), "-A7" : (0e6, 450e6),
"-I8" : (0e6, 362e6), "-I8" : (0e6, 362e6),
}[speedgrade] }[speedgrade]
# Intel / Max10 ------------------------------------------------------------------------------------
class Max10PLL(IntelClocking):
nclkouts_max = 5
n_div_range = (1, 512+1)
m_div_range = (1, 512+1)
c_div_range = (1, 512+1)
clkin_freq_range = (5e6, 472.5e6)
clkin_pfd_freq_range = (5e6, 325e6) # FIXME: use
vco_freq_range = (600e6, 1300e6)
def __init__(self, speedgrade="-6"):
self.logger = logging.getLogger("Max10PLL")
self.logger.info("Creating Max10PLL, {}.".format(colorer("speedgrade {}".format(speedgrade))))
IntelClocking.__init__(self)
self.clko_freq_range = {
"-6" : (0e6, 472.5e6),
"-7" : (0e6, 450e6),
"-8" : (0e6, 402.5e6),
}[speedgrade]