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soc_core: Fix l2_size argument handling.

This commit is contained in:
Florent Kermarrec 2022-03-22 11:17:05 +01:00
parent f0bd7019cd
commit 153f9f3660
2 changed files with 7 additions and 5 deletions
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2
litex/soc/integration/soc.py
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@ -1489,10 +1489,10 @@ class LiteXSoC(SoC):
l2_cache = FullMemoryWE()(l2_cache) l2_cache = FullMemoryWE()(l2_cache)
self.submodules.l2_cache = l2_cache self.submodules.l2_cache = l2_cache
litedram_wb = self.l2_cache.slave litedram_wb = self.l2_cache.slave
self.add_config("L2_SIZE", l2_cache_size)
else: else:
litedram_wb = wishbone.Interface(port.data_width) litedram_wb = wishbone.Interface(port.data_width)
self.submodules += wishbone.Converter(wb_sdram, litedram_wb) self.submodules += wishbone.Converter(wb_sdram, litedram_wb)
self.add_config("L2_SIZE", l2_cache_size)
# Wishbone Slave <--> LiteDRAM bridge. # Wishbone Slave <--> LiteDRAM bridge.
self.submodules.wishbone_bridge = LiteDRAMWishbone2Native( self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(

6
litex/soc/integration/soc_core.py
View File

@ -346,8 +346,10 @@ def soc_core_args(parser):
def soc_core_argdict(args): def soc_core_argdict(args):
r = dict() r = dict()
# Iterate on all SoCCore arguments. # Iterate on all arguments.
for a in inspect.getfullargspec(SoCCore.__init__).args: soc_args = inspect.getfullargspec(SoCCore.__init__).args
full_args = soc_args + ["l2_size"]
for a in full_args:
# Exclude specific arguments. # Exclude specific arguments.
if a in ["self", "platform"]: if a in ["self", "platform"]:
continue continue