soc_core: Fix l2_size argument handling.

litex/soc/integration/soc.py

@@ -1489,10 +1489,10 @@ class LiteXSoC(SoC):
                     l2_cache = FullMemoryWE()(l2_cache)
                 self.submodules.l2_cache = l2_cache
                 litedram_wb = self.l2_cache.slave
+                self.add_config("L2_SIZE", l2_cache_size)
             else:
                 litedram_wb = wishbone.Interface(port.data_width)
                 self.submodules += wishbone.Converter(wb_sdram, litedram_wb)
-            self.add_config("L2_SIZE", l2_cache_size)
 
             # Wishbone Slave <--> LiteDRAM bridge.
             self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(

litex/soc/integration/soc_core.py

@@ -346,8 +346,10 @@ def soc_core_args(parser):
 
 def soc_core_argdict(args):
     r = dict()
-    # Iterate on all SoCCore arguments.
-    for a in inspect.getfullargspec(SoCCore.__init__).args:
+    # Iterate on all arguments.
+    soc_args  = inspect.getfullargspec(SoCCore.__init__).args
+    full_args = soc_args + ["l2_size"]
+    for a in full_args:
         # Exclude specific arguments.
         if a in ["self", "platform"]:
             continue