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soc/integration/soc_sdram: add assertion on csr_data_width since BIOS only support SDRAM initialization for csr_data_width=8

This commit is contained in:
Florent Kermarrec 2018-07-19 12:51:16 +02:00
parent ae62fe076c
commit 1564b440eb
1 changed files with 2 additions and 0 deletions
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litex/soc/integration/soc_sdram.py
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@ -37,6 +37,8 @@ class SoCSDRAM(SoCCore):
def __init__(self, platform, clk_freq, l2_size=8192, **kwargs): def __init__(self, platform, clk_freq, l2_size=8192, **kwargs):
SoCCore.__init__(self, platform, clk_freq, **kwargs) SoCCore.__init__(self, platform, clk_freq, **kwargs)
if self.cpu_type is not None and self.csr_data_width != 8:
raise NotImplementedError("BIOS supports SDRAM initialization only for csr_data_width=8")
self.l2_size = l2_size self.l2_size = l2_size
self._sdram_phy = [] self._sdram_phy = []