Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

integration/soc: add auto_int type and use it on all int parameters. 

Allow passing parameters as int or hex values.
This commit is contained in:
Florent Kermarrec 2020-03-02 09:07:31 +01:00
parent 7e96c911b9
commit 156a85b15b
3 changed files with 17 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
litex/soc/integration/soc.py
View File

@ -27,6 +27,10 @@ from litex.soc.interconnect import axi
logging.basicConfig(level=logging.INFO) logging.basicConfig(level=logging.INFO)
# Helpers ------------------------------------------------------------------------------------------ # Helpers ------------------------------------------------------------------------------------------
def auto_int(x):
return int(x, 0)
def colorer(s, color="bright"): def colorer(s, color="bright"):
header = { header = {
"bright": "\x1b[1m", "bright": "\x1b[1m",

18
litex/soc/integration/soc_core.py
View File

@ -255,25 +255,25 @@ def soc_core_args(parser):
help="select CPU: {}, (default=vexriscv)".format(", ".join(iter(cpu.CPUS.keys())))) help="select CPU: {}, (default=vexriscv)".format(", ".join(iter(cpu.CPUS.keys()))))
parser.add_argument("--cpu-variant", default=None, parser.add_argument("--cpu-variant", default=None,
help="select CPU variant, (default=standard)") help="select CPU variant, (default=standard)")
parser.add_argument("--cpu-reset-address", default=None, type=int, parser.add_argument("--cpu-reset-address", default=None, type=auto_int,
help="CPU reset address (default=0x00000000 or ROM)") help="CPU reset address (default=0x00000000 or ROM)")
# ROM parameters # ROM parameters
parser.add_argument("--integrated-rom-size", default=0x8000, type=int, parser.add_argument("--integrated-rom-size", default=0x8000, type=auto_int,
help="size/enable the integrated (BIOS) ROM (default=32KB)") help="size/enable the integrated (BIOS) ROM (default=32KB)")
parser.add_argument("--integrated-rom-file", default=None, type=str, parser.add_argument("--integrated-rom-file", default=None, type=str,
help="integrated (BIOS) ROM binary file") help="integrated (BIOS) ROM binary file")
# SRAM parameters # SRAM parameters
parser.add_argument("--integrated-sram-size", default=0x1000, type=int, parser.add_argument("--integrated-sram-size", default=0x1000, type=auto_int,
help="size/enable the integrated SRAM (default=4KB)") help="size/enable the integrated SRAM (default=4KB)")
# MAIN_RAM parameters # MAIN_RAM parameters
parser.add_argument("--integrated-main-ram-size", default=None, type=int, parser.add_argument("--integrated-main-ram-size", default=None, type=auto_int,
help="size/enable the integrated main RAM") help="size/enable the integrated main RAM")
# CSR parameters # CSR parameters
parser.add_argument("--csr-data-width", default=None, type=int, parser.add_argument("--csr-data-width", default=None, type=auto_int,
help="CSR bus data-width (8 or 32, default=8)") help="CSR bus data-width (8 or 32, default=8)")
parser.add_argument("--csr-address-width", default=14, type=int, parser.add_argument("--csr-address-width", default=14, type=auto_int,
help="CSR bus address-width") help="CSR bus address-width")
parser.add_argument("--csr-paging", default=0x800, type=int, parser.add_argument("--csr-paging", default=0x800, type=auto_int,
help="CSR bus paging") help="CSR bus paging")
# Identifier parameters # Identifier parameters
parser.add_argument("--ident", default=None, type=str, parser.add_argument("--ident", default=None, type=str,
@ -285,9 +285,9 @@ def soc_core_args(parser):
help="with UART (default=True)") help="with UART (default=True)")
parser.add_argument("--uart-name", default="serial", type=str, parser.add_argument("--uart-name", default="serial", type=str,
help="UART type/name (default=serial)") help="UART type/name (default=serial)")
parser.add_argument("--uart-baudrate", default=None, type=int, parser.add_argument("--uart-baudrate", default=None, type=auto_int,
help="UART baudrate (default=115200)") help="UART baudrate (default=115200)")
parser.add_argument("--uart-fifo-depth", default=16, type=int, parser.add_argument("--uart-fifo-depth", default=16, type=auto_int,
help="UART FIFO depth (default=16)") help="UART FIFO depth (default=16)")
# Timer parameters # Timer parameters
parser.add_argument("--with-timer", default=None, type=bool, parser.add_argument("--with-timer", default=None, type=bool,

7
litex/soc/integration/soc_sdram.py
View File

@ -13,6 +13,7 @@ import inspect
from migen import * from migen import *
from litex.soc.integration.soc_core import * from litex.soc.integration.soc_core import *
from litex.soc.integration.soc import auto_int
__all__ = ["SoCSDRAM", "soc_sdram_args", "soc_sdram_argdict"] __all__ = ["SoCSDRAM", "soc_sdram_args", "soc_sdram_argdict"]
@ -52,13 +53,13 @@ class SoCSDRAM(SoCCore):
def soc_sdram_args(parser): def soc_sdram_args(parser):
soc_core_args(parser) soc_core_args(parser)
# L2 Cache # L2 Cache
parser.add_argument("--l2-size", default=8192, parser.add_argument("--l2-size", default=8192, type=auto_int,
help="L2 cache size (default=8192)") help="L2 cache size (default=8192)")
parser.add_argument("--min-l2-data-width", default=128, parser.add_argument("--min-l2-data-width", default=128, type=auto_int,
help="Minimum L2 cache datawidth (default=128)") help="Minimum L2 cache datawidth (default=128)")
# SDRAM # SDRAM
parser.add_argument("--max-sdram-size", default=0x40000000, parser.add_argument("--max-sdram-size", default=0x40000000, type=auto_int,
help="Maximum SDRAM size mapped to the SoC (default=1GB))") help="Maximum SDRAM size mapped to the SoC (default=1GB))")
def soc_sdram_argdict(args): def soc_sdram_argdict(args):