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targets/sim: generate analyzer.csv

This commit is contained in:
Florent Kermarrec 2018-09-20 12:20:48 +02:00
parent cde72603a1
commit 15e584d880
2 changed files with 31 additions and 22 deletions
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6
litex/boards/targets/sim.py
View File

@ -174,6 +174,7 @@ def main():
sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": "192.168.1.100"}) sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": "192.168.1.100"})
if args.with_etherbone: if args.with_etherbone:
sim_config.add_module('ethernet', "eth", args={"interface": "tap1", "ip": "192.168.1.101"}) sim_config.add_module('ethernet', "eth", args={"interface": "tap1", "ip": "192.168.1.101"})
soc = SimSoC( soc = SimSoC(
with_sdram=args.with_sdram, with_sdram=args.with_sdram,
with_ethernet=args.with_ethernet, with_ethernet=args.with_ethernet,
@ -182,7 +183,10 @@ def main():
**soc_kwargs) **soc_kwargs)
builder_kwargs["csr_csv"] = "csr.csv" builder_kwargs["csr_csv"] = "csr.csv"
builder = Builder(soc, **builder_kwargs) builder = Builder(soc, **builder_kwargs)
builder.build(sim_config=sim_config) vns = builder.build(run=False, sim_config=sim_config)
if args.with_analyzer:
soc.analyzer.export_csv(vns, "analyzer.csv")
builder.build(build=False, sim_config=sim_config)
if __name__ == "__main__": if __name__ == "__main__":

47
litex/build/sim/verilator.py
View File

@ -145,35 +145,40 @@ def _run_sim(build_name, as_root=False):
class SimVerilatorToolchain: class SimVerilatorToolchain:
def build(self, platform, fragment, build_dir="build", build_name="dut", def build(self, platform, fragment, build_dir="build", build_name="dut",
toolchain_path=None, serial="console", run=True, verbose=True, toolchain_path=None, serial="console", build=True, run=True, verbose=True,
sim_config=None): sim_config=None):
os.makedirs(build_dir, exist_ok=True) os.makedirs(build_dir, exist_ok=True)
os.chdir(build_dir) os.chdir(build_dir)
if not isinstance(fragment, _Fragment): if build:
fragment = fragment.get_fragment() if not isinstance(fragment, _Fragment):
platform.finalize(fragment) fragment = fragment.get_fragment()
platform.finalize(fragment)
v_output = platform.get_verilog(fragment, name=build_name) v_output = platform.get_verilog(fragment,
named_sc, named_pc = platform.resolve_signals(v_output.ns) name=build_name, dummy_signal=False, regular_comb=False, blocking_assign=True)
v_output.write(build_name + ".v") named_sc, named_pc = platform.resolve_signals(v_output.ns)
v_output.write(build_name + ".v")
include_paths = [] include_paths = []
for source in platform.sources: for source in platform.sources:
path = os.path.dirname(source[0]).replace("\\", "\/") path = os.path.dirname(source[0]).replace("\\", "\/")
if path not in include_paths: if path not in include_paths:
include_paths.append(path) include_paths.append(path)
include_paths += platform.verilog_include_paths include_paths += platform.verilog_include_paths
_generate_sim_h(platform) _generate_sim_h(platform)
_generate_sim_cpp(platform) _generate_sim_cpp(platform)
_generate_sim_variables(include_paths) _generate_sim_variables(include_paths)
if sim_config: if sim_config:
_generate_sim_config(sim_config) _generate_sim_config(sim_config)
_build_sim(platform, build_name, verbose)
_build_sim(platform, build_name, verbose)
if run: if run:
_run_sim(build_name, as_root=sim_config.has_module("ethernet")) _run_sim(build_name, as_root=sim_config.has_module("ethernet"))
os.chdir("..") os.chdir("../../")
return v_output.ns if build:
return v_output.ns