interconnect/axi/axi_full: Add region signal to aw/ar and optional user signal to aw/w/b/ar/r channels.
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@ -18,53 +18,73 @@ from litex.soc.interconnect.axi.axi_common import *
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# AXI Definition -----------------------------------------------------------------------------------
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# AXI Definition -----------------------------------------------------------------------------------
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def ax_description(address_width, id_width):
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def ax_description(address_width, id_width=0, user_width=0):
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return [
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# * present for interconnect with others cores but not used by LiteX.
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("addr", address_width),
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ax = [
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("burst", 2), # Burst type
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("addr", address_width), # Address Width.
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("len", 8), # Number of data (-1) transfers (up to 256)
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("burst", 2), # Burst type.
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("size", 4), # Number of bytes (-1) of each data transfer (up to 1024 bits)
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("len", 8), # Number of data (-1) transfers (up to 256).
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("size", 4), # Number of bytes (-1) of each data transfer (up to 1024 bits).
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("lock", 2), # *
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("lock", 2), # *
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("prot", 3), # *
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("prot", 3), # *
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("cache", 4), # *
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("cache", 4), # *
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("qos", 4), # *
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("qos", 4), # *
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("id", id_width)
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("region", 4), # *
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]
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]
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# * present for interconnect with others cores but not used by LiteX.
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if id_width:
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ax += [("id", id_width)] # ID Width.
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if user_width:
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ax += [("user", user_width)] # *
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return ax
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def w_description(data_width, id_width):
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def w_description(data_width, id_width=0, user_width=0):
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return [
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w = [
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("data", data_width),
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("data", data_width),
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("strb", data_width//8),
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("strb", data_width//8),
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("id", id_width)
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]
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]
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if id_width:
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w += [("id", id_width)]
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if user_width:
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w += [("user", user_width)]
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return w
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def b_description(id_width):
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def b_description(id_width=0, user_width=0):
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return [
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b = [("resp", 2)]
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("resp", 2),
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if id_width:
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("id", id_width)
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b += [("id", id_width)]
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]
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if user_width:
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b += [("user", user_width)]
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return b
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def r_description(data_width, id_width):
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def r_description(data_width, id_width=0, user_width=0):
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return [
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r = [
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("resp", 2),
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("resp", 2),
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("data", data_width),
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("data", data_width),
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("id", id_width)
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]
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]
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if id_width:
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r += [("id", id_width)]
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if user_width:
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r += [("user", user_width)]
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return r
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class AXIInterface:
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class AXIInterface:
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def __init__(self, data_width=32, address_width=32, id_width=1, clock_domain="sys", name=None, bursting=False):
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def __init__(self, data_width=32, address_width=32, id_width=1, clock_domain="sys", name=None, bursting=False,
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aw_user_width = 0,
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w_user_width = 0,
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b_user_width = 0,
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ar_user_width = 0,
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r_user_width = 0):
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self.data_width = data_width
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self.data_width = data_width
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self.address_width = address_width
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self.address_width = address_width
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self.id_width = id_width
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self.id_width = id_width
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self.clock_domain = clock_domain
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self.clock_domain = clock_domain
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self.bursting = bursting # FIXME: Use or add check.
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self.bursting = bursting # FIXME: Use or add check.
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self.aw = stream.Endpoint(ax_description(address_width, id_width), name=name)
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self.aw = stream.Endpoint(ax_description(address_width, id_width, aw_user_width), name=name)
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self.w = stream.Endpoint(w_description(data_width, id_width), name=name)
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self.w = stream.Endpoint(w_description(data_width, id_width, w_user_width), name=name)
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self.b = stream.Endpoint(b_description(id_width), name=name)
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self.b = stream.Endpoint(b_description(id_width, b_user_width), name=name)
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self.ar = stream.Endpoint(ax_description(address_width, id_width), name=name)
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self.ar = stream.Endpoint(ax_description(address_width, id_width, ar_user_width), name=name)
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self.r = stream.Endpoint(r_description(data_width, id_width), name=name)
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self.r = stream.Endpoint(r_description(data_width, id_width, r_user_width), name=name)
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def connect_to_pads(self, pads, mode="master"):
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def connect_to_pads(self, pads, mode="master"):
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return connect_to_pads(self, pads, mode, axi_full=True)
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return connect_to_pads(self, pads, mode, axi_full=True)
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