cpu/vexriscv/cpu-count: fix type and add comment (thanks dayjaby).
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@ -8,9 +8,10 @@
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import os
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from os import path
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from litex import get_data_mod
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from migen import *
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from litex import get_data_mod
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect.csr import *
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from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
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@ -49,7 +50,7 @@ class VexRiscvSMP(CPU):
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@staticmethod
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def args_fill(parser):
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parser.add_argument("--cpu-count", default=1, help="")
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parser.add_argument("--cpu-count", default=1, help="Number of CPU(s) in the cluster.", type=int)
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parser.add_argument("--with-coherent-dma", action='store_true', help="Enable Coherent DMA Slave interface.")
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parser.add_argument("--without-coherent-dma", action='store_true', help="Disable Coherent DMA Slave interface.")
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parser.add_argument("--dcache-width", default=None, help="L1 data cache bus width.")
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