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cpu/vexriscv/cpu-count: fix type and add comment (thanks dayjaby).

This commit is contained in:
Florent Kermarrec 2021-01-04 14:40:49 +01:00
parent f31f9a20f0
commit 16008d3f3a
1 changed files with 3 additions and 2 deletions
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5
litex/soc/cores/cpu/vexriscv_smp/core.py
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@ -8,9 +8,10 @@
import os import os
from os import path from os import path
from litex import get_data_mod
from migen import * from migen import *
from litex import get_data_mod
from litex.soc.interconnect import wishbone from litex.soc.interconnect import wishbone
from litex.soc.interconnect.csr import * from litex.soc.interconnect.csr import *
from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32 from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
@ -49,7 +50,7 @@ class VexRiscvSMP(CPU):
@staticmethod @staticmethod
def args_fill(parser): def args_fill(parser):
parser.add_argument("--cpu-count", default=1, help="") parser.add_argument("--cpu-count", default=1, help="Number of CPU(s) in the cluster.", type=int)
parser.add_argument("--with-coherent-dma", action='store_true', help="Enable Coherent DMA Slave interface.") parser.add_argument("--with-coherent-dma", action='store_true', help="Enable Coherent DMA Slave interface.")
parser.add_argument("--without-coherent-dma", action='store_true', help="Disable Coherent DMA Slave interface.") parser.add_argument("--without-coherent-dma", action='store_true', help="Disable Coherent DMA Slave interface.")
parser.add_argument("--dcache-width", default=None, help="L1 data cache bus width.") parser.add_argument("--dcache-width", default=None, help="L1 data cache bus width.")