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cpu/rocket: fix variant typos 

The `fulld` and `fullq` variants point to the wrong (`LitexFullConfig`)
verilog. Fix by pointing to the correct code (`LitexFullDConfig` and
`LitexFullQConfig`, respectively).

Reported-by: Ioannis Ioannou <roryt@roryt.gr>
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
This commit is contained in:
Gabriel Somlo 2022-09-20 09:29:46 -04:00
parent e12af4f050
commit 162a0a4c1e
1 changed files with 2 additions and 2 deletions
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4
litex/soc/cores/cpu/rocket/core.py
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@ -51,9 +51,9 @@ CPU_VARIANTS = {
"linuxq": "freechips.rocketchip.system.LitexLinuxQConfig",
"linux2q": "freechips.rocketchip.system.LitexLinux2QConfig",
"full": "freechips.rocketchip.system.LitexFullConfig",
"fulld": "freechips.rocketchip.system.LitexFullConfig",
"fulld": "freechips.rocketchip.system.LitexFullDConfig",
"full4d": "freechips.rocketchip.system.LitexFull4DConfig",
"fullq": "freechips.rocketchip.system.LitexFullConfig",
"fullq": "freechips.rocketchip.system.LitexFullQConfig",
"full4q": "freechips.rocketchip.system.LitexFull4QConfig",
}