soc/cores/clock: initial GW5A support
GW5A has different PLLs than GW1N/GW2A, with multiple individual ODIV's. GW5A-25 has a different PLL with GW5A[S]T-138, with lack of dynamic control. Add basic support for them. Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
This commit is contained in:
Icenowy Zheng
parent
82602f660c
commit
1636c0ef8d
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2021-2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.gen import *
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from litex.soc.cores.clock.common import *
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# GoWin / GW5APLL ----------------------------------------------------------------------------------
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class GW5APLL(LiteXModule):
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nclkouts_max = 7
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def __init__(self, devicename, device, vco_margin=0):
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self.logger = logging.getLogger("GW5APLL")
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self.logger.info("Creating GW5APLL.".format())
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self.device = device
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self.devicename = devicename
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self.vco_margin = vco_margin
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self.reset = Signal()
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self.locked = Signal()
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self.clkin_freq = None
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self.vcxo_freq = None
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self.nclkouts = 0
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self.clkouts = {}
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self.config = {}
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self.params = {}
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self.vco_freq_range = self.get_vco_freq_range(device)
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self.pfd_freq_range = self.get_pfd_freq_range(device)
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@staticmethod
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def get_vco_freq_range(device):
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vco_freq_range = None
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if device.startswith('GW5A-') or device.startswith('GW5AT-') or device.startswith('GW5AST-'):
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vco_freq_range = (800e6, 2000e6) # datasheet values
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if vco_freq_range is None:
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raise ValueError(f"Unsupported device {device}.")
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return vco_freq_range
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@staticmethod
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def get_pfd_freq_range(device):
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pfd_freq_range = None
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if device.startswith('GW5A-') or device.startswith('GW5AT-') or device.startswith('GW5AST-'):
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pfd_freq_range = (10e6, 400e6) # datasheet values
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if pfd_freq_range is None:
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raise ValueError(f"Unsupported device {device}.")
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return pfd_freq_range
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def register_clkin(self, clkin, freq):
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self.clkin = Signal()
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if isinstance(clkin, (Signal, ClockSignal)):
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self.comb += self.clkin.eq(clkin)
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else:
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raise ValueError
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self.clkin_freq = freq
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register_clkin_log(self.logger, clkin, freq)
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def create_clkout(self, cd, freq, phase=0, margin=1e-2, with_reset=True):
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assert self.nclkouts < self.nclkouts_max
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clkout = Signal()
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self.clkouts[self.nclkouts] = (clkout, freq, phase, margin)
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if with_reset:
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self.specials += AsyncResetSynchronizer(cd, ~self.locked)
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self.comb += cd.clk.eq(clkout)
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create_clkout_log(self.logger, cd.name, freq, margin, self.nclkouts)
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self.nclkouts += 1
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def compute_config(self):
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configs = [] # corresponding VCO/FBDIV/IDIV/ODIV params + diff
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for idiv in range(1, 64):
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pfd_freq = self.clkin_freq/idiv
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pfd_freq_min, pfd_freq_max = self.pfd_freq_range
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if (pfd_freq < pfd_freq_min) or (pfd_freq > pfd_freq_max):
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continue
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for fdiv in range(1, 64):
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for mdiv in range(2,128):
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vco_freq = self.clkin_freq/idiv*fdiv*mdiv
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(vco_freq_min, vco_freq_max) = self.vco_freq_range
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if (vco_freq >= vco_freq_min*(1 + self.vco_margin) and
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vco_freq <= vco_freq_max*(1 - self.vco_margin)):
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okay = True
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config = {}
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for n, (clk, f, p, m) in self.clkouts.items():
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odiv = round(vco_freq/f)
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out_freq = vco_freq/odiv
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diff = abs(out_freq - f) / f
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pe = round(p * odiv / 360)
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if abs((360.0 * pe / odiv) - p) / 360 > m:
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okay = False
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if diff > m:
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okay = False
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else:
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config["odiv%d" % n] = odiv
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config["diff%d" % n] = diff
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config["pe%d" % n] = int(p * odiv / 360)
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config["pe%d_fine" % n] = round(p * odiv * 8 / 360) % 8
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if okay:
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config["idiv"] = idiv
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config["vco"] = vco_freq
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config["fdiv"] = fdiv
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config["mdiv"] = mdiv
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configs += [config]
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if len(configs) == 0:
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raise ValueError("No PLL config found")
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best_config = None
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best_diff_sum = 0
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for i in range(0,len(configs)):
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curr_diff_sum = 0
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for n, clkout in self.clkouts.items():
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curr_diff_sum += configs[i]["diff%d" % n]
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if i == 0 or curr_diff_sum < best_diff_sum:
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best_diff_sum = curr_diff_sum
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best_config = configs[i]
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return best_config
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def do_finalize(self):
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assert hasattr(self, "clkin")
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assert len(self.clkouts) > 0 and len(self.clkouts) <= self.nclkouts_max
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config = self.compute_config()
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# Based on UG306-1.0 Note.
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self.params.update(
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# Parameters.
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p_FCLKIN = str(self.clkin_freq/1e6), # Clk Input frequency (MHz).
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p_IDIV_SEL = config["idiv"], # Static IDIV value (1-64).
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p_FBDIV_SEL = config["fdiv"], # Static FBDIV value (1-64).
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p_ODIV0_SEL = 8, # Static ODIV value (1-128).
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p_ODIV0_FRAC_SEL = 0, # Static ODIV0 fractional value (0-7)/8
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p_ODIV1_SEL = 8, # Static ODIV1 value
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p_ODIV2_SEL = 8, # Static ODIV2 value
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p_ODIV3_SEL = 8, # Static ODIV3 value
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p_ODIV4_SEL = 8, # Static ODIV4 value
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p_ODIV5_SEL = 8, # Static ODIV5 value
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p_ODIV6_SEL = 8, # Static ODIV6 value
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p_MDIV_SEL = config["mdiv"], # Static MDIV value (2-128).
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p_MDIV_FRAC_SEL = 0, # Static MDIV fractional value (0-7)/8
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p_CLKOUT0_EN = "FALSE", # Disable CLKOUT0.
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p_CLKOUT1_EN = "FALSE", # Disable CLKOUT1.
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p_CLKOUT2_EN = "FALSE", # Disable CLKOUT2.
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p_CLKOUT3_EN = "FALSE", # Disable CLKOUT3.
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p_CLKOUT4_EN = "FALSE", # Disable CLKOUT4.
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p_CLKOUT5_EN = "FALSE", # Disable CLKOUT5.
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p_CLKOUT6_EN = "FALSE", # Disable CLKOUT6.
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p_CLKOUT0_DT_DIR = 1, # Static CLKOUT0 duty control direction (0-down, 1-up)
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p_CLKOUT1_DT_DIR = 1, # Static CLKOUT1 duty control direction (0-down, 1-up)
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p_CLKOUT2_DT_DIR = 1, # Static CLKOUT2 duty control direction (0-down, 1-up)
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p_CLKOUT3_DT_DIR = 1, # Static CLKOUT3 duty control direction (0-down, 1-up)
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p_CLKOUT0_DT_STEP = 0, # Static CLKOUT0 duty control step (0,1,2,4)*50ps
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p_CLKOUT1_DT_STEP = 0, # Static CLKOUT1 duty control step (0,1,2,4)*50ps
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p_CLKOUT2_DT_STEP = 0, # Static CLKOUT2 duty control step (0,1,2,4)*50ps
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p_CLKOUT3_DT_STEP = 0, # Static CLKOUT3 duty control step (0,1,2,4)*50ps
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p_CLK0_IN_SEL = 0, # Select ODIV0 source (0-VCO, 1-CLKIN)
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p_CLK0_OUT_SEL = 0, # Select CLKOUT0 source (0-ODIV0, 1-CLKIN)
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p_CLK1_IN_SEL = 0, # Select ODIV1 source (0-VCO, 1-CLKIN)
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p_CLK1_OUT_SEL = 0, # Select CLKOUT1 source (0-ODIV1, 1-CLKIN)
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p_CLK2_IN_SEL = 0, # Select ODIV2 source (0-VCO, 1-CLKIN)
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p_CLK2_OUT_SEL = 0, # Select CLKOUT2 source (0-ODIV2, 1-CLKIN)
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p_CLK3_IN_SEL = 0, # Select ODIV3 source (0-VCO, 1-CLKIN)
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p_CLK3_OUT_SEL = 0, # Select CLKOUT3 source (0-ODIV3, 1-CLKIN)
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p_CLK4_IN_SEL = 0, # Select ODIV4 source (0-VCO, 1-CLKIN)
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p_CLK4_OUT_SEL = 0, # Select CLKOUT4 source (0-ODIV4, 1-CLKIN)
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p_CLK5_IN_SEL = 0, # Select ODIV5 source (0-VCO, 1-CLKIN)
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p_CLK5_OUT_SEL = 0, # Select CLKOUT5 source (0-ODIV5, 1-CLKIN)
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p_CLKFB_SEL = "INTERNAL", # Clk Feedback type (INTERNAL, EXTERNAL).
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p_DYN_DPA_EN = "FALSE", # Disable dynamic phase shift.
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p_CLKOUT0_PE_COARSE= 0, # Static CLKOUT0 phase shift coarse config
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p_CLKOUT0_PE_FINE = 0, # Static CLKOUT0 phase shift fine config
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p_CLKOUT1_PE_COARSE= 0, # Static CLKOUT1 phase shift coarse config
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p_CLKOUT1_PE_FINE = 0, # Static CLKOUT1 phase shift fine config
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p_CLKOUT2_PE_COARSE= 0, # Static CLKOUT2 phase shift coarse config
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p_CLKOUT2_PE_FINE = 0, # Static CLKOUT2 phase shift fine config
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p_CLKOUT3_PE_COARSE= 0, # Static CLKOUT3 phase shift coarse config
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p_CLKOUT3_PE_FINE = 0, # Static CLKOUT3 phase shift fine config
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p_CLKOUT4_PE_COARSE= 0, # Static CLKOUT4 phase shift coarse config
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p_CLKOUT4_PE_FINE = 0, # Static CLKOUT4 phase shift fine config
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p_CLKOUT5_PE_COARSE= 0, # Static CLKOUT5 phase shift coarse config
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p_CLKOUT5_PE_FINE = 0, # Static CLKOUT5 phase shift fine config
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p_CLKOUT6_PE_COARSE= 0, # Static CLKOUT6 phase shift coarse config
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p_CLKOUT6_PE_FINE = 0, # Static CLKOUT6 phase shift fine config
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p_DYN_PE0_SEL = "FALSE", # Static CLKOUT0 phase shift.
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p_DYN_PE1_SEL = "FALSE", # Static CLKOUT1 phase shift.
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p_DYN_PE2_SEL = "FALSE", # Static CLKOUT2 phase shift.
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p_DYN_PE3_SEL = "FALSE", # Static CLKOUT3 phase shift.
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p_DYN_PE4_SEL = "FALSE", # Static CLKOUT4 phase shift.
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p_DYN_PE5_SEL = "FALSE", # Static CLKOUT5 phase shift.
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p_DYN_PE6_SEL = "FALSE", # Static CLKOUT6 phase shift.
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p_DE0_EN = "FALSE", # Disable CLKOUT0 duty cycle adjust
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p_DE1_EN = "FALSE", # Disable CLKOUT0 duty cycle adjust
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p_DE2_EN = "FALSE", # Disable CLKOUT0 duty cycle adjust
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p_DE3_EN = "FALSE", # Disable CLKOUT0 duty cycle adjust
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p_DE4_EN = "FALSE", # Disable CLKOUT0 duty cycle adjust
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p_DE5_EN = "FALSE", # Disable CLKOUT0 duty cycle adjust
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p_DE6_EN = "FALSE", # Disable CLKOUT0 duty cycle adjust
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p_RESET_I_EN = "FALSE", # -
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p_RESET_O_EN = "FALSE", # -
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p_SSC_EN = "FALSE", # Disable spread spectrun control.
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# Inputs.
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i_CLKIN = self.clkin, # Clk Input.
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i_CLKFB = 0, # Clk Feedback.
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i_RESET = self.reset, # PLL Reset.
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i_PLLPWD = 0, # PLL Power Down.
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i_RESET_I = 0, # PLL Partial Reset (for testing)
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i_RESET_O = 0, # PLL Partial Reset (for testing)
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i_PSDIR = 0, # Dynamic Phase Select direction.
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i_PSSEL = Constant(0, 3), # Dynamic Phase Select channel control.
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i_PSPULSE = 0, # Dynamic Phase Select pulse.
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i_SSCPOL = 0, # Spread Spectrum polarity.
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i_SSCON = 0, # Spread Spectrum enable.
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i_SSCMDSEL = Constant(0, 7), # Dynamic SSC MDIV integer control.
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i_SSCMDSEL_FRAC = Constant(0, 3), # Dynamic SSC MDIV fractional control.
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o_LOCK = self.locked,
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o_CLKOUT0 = Open(),
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o_CLKOUT1 = Open(),
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o_CLKOUT2 = Open(),
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o_CLKOUT3 = Open(),
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o_CLKOUT4 = Open(),
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o_CLKOUT5 = Open(),
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o_CLKOUT6 = Open(),
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o_CLKFBOUT = Open()
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)
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if self.device.startswith('GW5A-'): # GW5A-25, uses PLLA
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instance_name = 'PLLA'
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self.params.update(
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i_MDCLK = 0,
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i_MDOPC = Constant(0, 2),
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i_MDAINC = 0,
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i_MDWDI = Constant(0, 8),
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)
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else: # GW5A{,S}T, uses PLL
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instance_name = 'PLL'
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self.params.update(
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p_DYN_IDIV_SEL = "FALSE", # Disable dynamic IDIV.
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p_DYN_FBDIV_SEL = "FALSE", # Disable dynamic FBDIV.
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p_DYN_ODIV0_SEL = "FALSE", # Disable dynamic ODIV0.
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p_DYN_ODIV1_SEL = "FALSE", # Disable dynamic ODIV1.
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p_DYN_ODIV2_SEL = "FALSE", # Disable dynamic ODIV2.
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p_DYN_ODIV3_SEL = "FALSE", # Disable dynamic ODIV3.
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p_DYN_ODIV4_SEL = "FALSE", # Disable dynamic ODIV4.
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p_DYN_ODIV5_SEL = "FALSE", # Disable dynamic ODIV5.
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p_DYN_ODIV6_SEL = "FALSE", # Disable dynamic ODIV6.
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p_DYN_DT0_SEL = "FALSE", # Static CLKOUT0 duty control.
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p_DYN_DT1_SEL = "FALSE", # Static CLKOUT1 duty control.
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p_DYN_DT2_SEL = "FALSE", # Static CLKOUT2 duty control.
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p_DYN_DT3_SEL = "FALSE", # Static CLKOUT3 duty control.
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p_DYN_ICP_SEL = "FALSE", # Static ICP_SEL.
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# ICP_SEL determined by the toolchain
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p_DYN_LPF_SEL = "FALSE", # Static LPF_RES/LPF_CAP;
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# LPF_RES/LPF_CAP determined by the toolchain
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i_FBDSEL = Constant(0, 6), # Dynamic FBDIV control.
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i_IDSEL = Constant(0, 6), # Dynamic IDIV control.
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i_MDSEL = Constant(0, 7), # Dynamic MDIV integer control.
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i_MDSEL_FRAC = Constant(0, 3), # Dynamic MDIV fractional control.
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i_ODSEL0 = Constant(0, 7), # Dynamic ODIV0 integer control.
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i_ODSEL0_FRAC = Constant(0, 3), # Dynamic ODIV0 fractional control.
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i_ODSEL1 = Constant(0, 7), # Dynamic ODIV1 control.
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i_ODSEL2 = Constant(0, 7), # Dynamic ODIV2 control.
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i_ODSEL3 = Constant(0, 7), # Dynamic ODIV3 control.
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i_ODSEL4 = Constant(0, 7), # Dynamic ODIV4 control.
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i_ODSEL5 = Constant(0, 7), # Dynamic ODIV5 control.
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i_ODSEL6 = Constant(0, 7), # Dynamic ODIV6 control.
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i_DT0 = Constant(0, 4), # Dynamic duty cycle control for CLKOUT0.
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i_DT1 = Constant(0, 4), # Dynamic duty cycle control for CLKOUT1.
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i_DT2 = Constant(0, 4), # Dynamic duty cycle control for CLKOUT2.
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i_DT3 = Constant(0, 4), # Dynamic duty cycle control for CLKOUT3.
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i_ENCLK0 = 1, # Dynamic CLKOUT0 enable.
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i_ENCLK1 = 1, # Dynamic CLKOUT1 enable.
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i_ENCLK2 = 1, # Dynamic CLKOUT2 enable.
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i_ENCLK3 = 1, # Dynamic CLKOUT3 enable.
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i_ENCLK4 = 1, # Dynamic CLKOUT4 enable.
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i_ENCLK5 = 1, # Dynamic CLKOUT5 enable.
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i_ENCLK6 = 1, # Dynamic CLKOUT6 enable.
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i_ICPSEL = Constant(0, 6), # Dynamic ICP current control.
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i_LPFRES = Constant(0, 3), # Dynamic LPFRES control.
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i_LPFCAP = Constant(0, 2), # Dynamic LPFCAP control.
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)
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for i in range(0, len(self.clkouts)):
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clk, f, p, m = self.clkouts[i]
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self.params["o_CLKOUT%d" % i] = clk
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self.params["p_CLKOUT%d_EN" % i] = "TRUE"
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self.params["p_ODIV%d_SEL" % i] = config["odiv%d" % i]
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self.params["p_CLKOUT%d_PE_COARSE" % i] = config["pe%d" % i]
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self.params["p_CLKOUT%d_PE_FINE" % i] = config["pe%d_fine" % i]
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self.specials += Instance(instance_name, **self.params)
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