soc_core: add csr range check
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6febb6826c
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@ -298,6 +298,10 @@ class SoCCore(Module):
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def get_memory_regions(self):
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def get_memory_regions(self):
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return self._memory_regions
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return self._memory_regions
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def check_csr_range(self, name, addr):
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if addr >= 1<<(self.csr_address_width+2):
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raise ValueError("{} CSR out of range, increase csr_address_width".format(name))
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def check_csr_region(self, name, origin):
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def check_csr_region(self, name, origin):
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for n, o, l, obj in self._csr_regions:
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for n, o, l, obj in self._csr_regions:
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if n == name or o == origin:
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if n == name or o == origin:
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@ -360,8 +364,10 @@ class SoCCore(Module):
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self.submodules.csrcon = csr_bus.Interconnect(
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self.submodules.csrcon = csr_bus.Interconnect(
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self.wishbone2csr.csr, self.csrbankarray.get_buses())
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self.wishbone2csr.csr, self.csrbankarray.get_buses())
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for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
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for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
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self.check_csr_range(name, 0x800*mapaddr)
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self.add_csr_region(name, (self.mem_map["csr"] + 0x800*mapaddr) | self.shadow_base, self.csr_data_width, csrs)
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self.add_csr_region(name, (self.mem_map["csr"] + 0x800*mapaddr) | self.shadow_base, self.csr_data_width, csrs)
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for name, memory, mapaddr, mmap in self.csrbankarray.srams:
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for name, memory, mapaddr, mmap in self.csrbankarray.srams:
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self.check_csr_range(name, 0x800*mapaddr)
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self.add_csr_region(name + "_" + memory.name_override, (self.mem_map["csr"] + 0x800*mapaddr) | self.shadow_base, self.csr_data_width, memory)
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self.add_csr_region(name + "_" + memory.name_override, (self.mem_map["csr"] + 0x800*mapaddr) | self.shadow_base, self.csr_data_width, memory)
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for name, constant in self.csrbankarray.constants:
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for name, constant in self.csrbankarray.constants:
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self._constants.append(((name + "_" + constant.name).upper(), constant.value.value))
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self._constants.append(((name + "_" + constant.name).upper(), constant.value.value))
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