Merge pull request #718 from trabucayre/zynq_fix_constraints

don't add pins without pad location in constraints file

litex/build/generic_platform.py

@@ -8,6 +8,7 @@
 
 import sys
 import os
+import re
 
 from migen.fhdl.structure import Signal, Cat
 from migen.genlib.record import Record
@@ -395,7 +396,8 @@ class GenericPlatform:
         # resolve signal names in constraints
         sc = self.constraint_manager.get_sig_constraints()
         named_sc = [(vns.get_name(sig), pins, others, resource)
-                    for sig, pins, others, resource in sc]
+                    for sig, pins, others, resource in sc
+                        if not re.match(r"^X+$", ''.join(pins))]
         # resolve signal names in platform commands
         pc = self.constraint_manager.get_platform_commands()
         named_pc = []