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i2s: Fix the incorrect TX fifo almost empty offset

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Pawel Sagan 2020-06-25 14:32:50 +02:00 committed by Mateusz Holenko
parent 8f204e7797
commit 16a0aebcad
1 changed files with 1 additions and 1 deletions
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litex/soc/cores/i2s.py
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@ -495,7 +495,7 @@ class S7I2S(Module, AutoCSR, AutoDoc):
p_DEVICE = "7SERIES", p_DEVICE = "7SERIES",
p_FIFO_SIZE = "18Kb", p_FIFO_SIZE = "18Kb",
p_DATA_WIDTH = fifo_data_width, p_DATA_WIDTH = fifo_data_width,
p_ALMOST_EMPTY_OFFSET = fifo_depth, p_ALMOST_EMPTY_OFFSET = (512 - fifo_depth),
p_ALMOST_FULL_OFFSET = 8, p_ALMOST_FULL_OFFSET = 8,
p_DO_REG = 0, p_DO_REG = 0,
i_CLK = ClockSignal(), i_CLK = ClockSignal(),