litex_sim: Allow regular_comb=False argument

This was removed in
3b78fd928d fhdl/verilog: Remove blocking_assign (not used with LiteX).

However that breaks litedram gen.py which passes regular_comb=False
to all toolchain builders

litex/build/sim/verilator.py

@@ -189,6 +189,7 @@ class SimVerilatorToolchain:
             trace_fst        = False,
             trace_start      = 0,
             trace_end        = -1,
+            regular_comb     = False,
             interactive      = True,
             pre_run_callback = None):
 
@@ -203,6 +204,9 @@ class SimVerilatorToolchain:
                 fragment = fragment.get_fragment()
             platform.finalize(fragment)
 
+            if regular_comb:
+                raise ValueError("SimVerilatorToolchain disallows regular_comb=True")
+
             # Generate verilog
             v_output = platform.get_verilog(fragment, name=build_name)
             named_sc, named_pc = platform.resolve_signals(v_output.ns)