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litex_sim: Allow regular_comb=False argument

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This was removed in
3b78fd928d fhdl/verilog: Remove blocking_assign (not used with LiteX).

However that breaks litedram gen.py which passes regular_comb=False
to all toolchain builders
This commit is contained in:
Matt Johnston 2021-11-02 12:00:50 +08:00
parent 9ecb1e61a9
commit 1716e37809
1 changed files with 4 additions and 0 deletions
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4
litex/build/sim/verilator.py
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@ -189,6 +189,7 @@ class SimVerilatorToolchain:
trace_fst = False, trace_fst = False,
trace_start = 0, trace_start = 0,
trace_end = -1, trace_end = -1,
regular_comb = False,
interactive = True, interactive = True,
pre_run_callback = None): pre_run_callback = None):
@ -203,6 +204,9 @@ class SimVerilatorToolchain:
fragment = fragment.get_fragment() fragment = fragment.get_fragment()
platform.finalize(fragment) platform.finalize(fragment)
if regular_comb:
raise ValueError("SimVerilatorToolchain disallows regular_comb=True")
# Generate verilog # Generate verilog
v_output = platform.get_verilog(fragment, name=build_name) v_output = platform.get_verilog(fragment, name=build_name)
named_sc, named_pc = platform.resolve_signals(v_output.ns) named_sc, named_pc = platform.resolve_signals(v_output.ns)