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cpu/vexriscv_smp: cleanup new args integration and fix cluster naming.

This commit is contained in:
Florent Kermarrec 2021-01-25 09:31:16 +01:00
parent 7fa03cb1f3
commit 17195c5e96
1 changed files with 39 additions and 40 deletions
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11
litex/soc/cores/cpu/vexriscv_smp/core.py
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@ -53,8 +53,8 @@ class VexRiscvSMP(CPU):
@staticmethod @staticmethod
def args_fill(parser): def args_fill(parser):
parser.add_argument("--cpu-count", default=1, help="Number of CPU(s) in the cluster.", type=int) parser.add_argument("--cpu-count", default=1, help="Number of CPU(s) in the cluster.", type=int)
parser.add_argument("--with-coherent-dma", action='store_true', help="Enable Coherent DMA Slave interface.") parser.add_argument("--with-coherent-dma", action="store_true", help="Enable Coherent DMA Slave interface.")
parser.add_argument("--without-coherent-dma", action='store_true', help="Disable Coherent DMA Slave interface.") parser.add_argument("--without-coherent-dma", action="store_true", help="Disable Coherent DMA Slave interface.")
parser.add_argument("--dcache-width", default=None, help="L1 data cache bus width.") parser.add_argument("--dcache-width", default=None, help="L1 data cache bus width.")
parser.add_argument("--icache-width", default=None, help="L1 instruction cache bus width.") parser.add_argument("--icache-width", default=None, help="L1 instruction cache bus width.")
parser.add_argument("--dcache-size", default=None, help="L1 data cache size in byte per CPU.") parser.add_argument("--dcache-size", default=None, help="L1 data cache size in byte per CPU.")
@ -62,8 +62,8 @@ class VexRiscvSMP(CPU):
parser.add_argument("--icache-size", default=None, help="L1 instruction cache size in byte per CPU.") parser.add_argument("--icache-size", default=None, help="L1 instruction cache size in byte per CPU.")
parser.add_argument("--icache-ways", default=None, help="L1 instruction cache ways per CPU") parser.add_argument("--icache-ways", default=None, help="L1 instruction cache ways per CPU")
parser.add_argument("--aes-instruction", default=None, help="Enable AES instruction acceleration.") parser.add_argument("--aes-instruction", default=None, help="Enable AES instruction acceleration.")
parser.add_argument("--without-out-of-order-decoder", action='store_true', help="Reduce area at cost of peripheral access speed") parser.add_argument("--without-out-of-order-decoder", action="store_true", help="Reduce area at cost of peripheral access speed")
parser.add_argument("--with-wishbone-memory" , action='store_true', help="Disable native litedram interface") parser.add_argument("--with-wishbone-memory" , action="store_true", help="Disable native LiteDRAM interface")
@staticmethod @staticmethod
def args_read(args): def args_read(args):
@ -120,8 +120,7 @@ class VexRiscvSMP(CPU):
f"Dw{VexRiscvSMP.dcache_width}" \ f"Dw{VexRiscvSMP.dcache_width}" \
f"Ds{VexRiscvSMP.dcache_size}" \ f"Ds{VexRiscvSMP.dcache_size}" \
f"Dy{VexRiscvSMP.dcache_ways}" \ f"Dy{VexRiscvSMP.dcache_ways}" \
"_" \ f"{'_'+ldw if not VexRiscvSMP.wishbone_memory else ''}" \
f"{ldw if not VexRiscvSMP.wishbone_memory else ''}" \
f"{'_Cdma' if VexRiscvSMP.coherent_dma else ''}" \ f"{'_Cdma' if VexRiscvSMP.coherent_dma else ''}" \
f"{'_Aes' if VexRiscvSMP.aes_instruction else ''}" \ f"{'_Aes' if VexRiscvSMP.aes_instruction else ''}" \
f"{'_Ood' if VexRiscvSMP.out_of_order_decoder else ''}" \ f"{'_Ood' if VexRiscvSMP.out_of_order_decoder else ''}" \