cpu/vexriscv_smp: cleanup new args integration and fix cluster naming.
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@ -37,33 +37,33 @@ class VexRiscvSMP(CPU):
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nop = "nop"
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nop = "nop"
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io_regions = {0x80000000: 0x80000000} # origin, length
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io_regions = {0x80000000: 0x80000000} # origin, length
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cpu_count = 1
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cpu_count = 1
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dcache_size = 4096
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dcache_size = 4096
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icache_size = 4096
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icache_size = 4096
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dcache_ways = 1
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dcache_ways = 1
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icache_ways = 1
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icache_ways = 1
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coherent_dma = False
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coherent_dma = False
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litedram_width = 32
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litedram_width = 32
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dcache_width = 32
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dcache_width = 32
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icache_width = 32
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icache_width = 32
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aes_instruction = False
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aes_instruction = False
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out_of_order_decoder = True
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out_of_order_decoder = True
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wishbone_memory = False
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wishbone_memory = False
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@staticmethod
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@staticmethod
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def args_fill(parser):
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def args_fill(parser):
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parser.add_argument("--cpu-count", default=1, help="Number of CPU(s) in the cluster.", type=int)
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parser.add_argument("--cpu-count", default=1, help="Number of CPU(s) in the cluster.", type=int)
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parser.add_argument("--with-coherent-dma", action='store_true', help="Enable Coherent DMA Slave interface.")
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parser.add_argument("--with-coherent-dma", action="store_true", help="Enable Coherent DMA Slave interface.")
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parser.add_argument("--without-coherent-dma", action='store_true', help="Disable Coherent DMA Slave interface.")
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parser.add_argument("--without-coherent-dma", action="store_true", help="Disable Coherent DMA Slave interface.")
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parser.add_argument("--dcache-width", default=None, help="L1 data cache bus width.")
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parser.add_argument("--dcache-width", default=None, help="L1 data cache bus width.")
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parser.add_argument("--icache-width", default=None, help="L1 instruction cache bus width.")
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parser.add_argument("--icache-width", default=None, help="L1 instruction cache bus width.")
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parser.add_argument("--dcache-size", default=None, help="L1 data cache size in byte per CPU.")
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parser.add_argument("--dcache-size", default=None, help="L1 data cache size in byte per CPU.")
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parser.add_argument("--dcache-ways", default=None, help="L1 data cache ways per CPU.")
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parser.add_argument("--dcache-ways", default=None, help="L1 data cache ways per CPU.")
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parser.add_argument("--icache-size", default=None, help="L1 instruction cache size in byte per CPU.")
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parser.add_argument("--icache-size", default=None, help="L1 instruction cache size in byte per CPU.")
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parser.add_argument("--icache-ways", default=None, help="L1 instruction cache ways per CPU")
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parser.add_argument("--icache-ways", default=None, help="L1 instruction cache ways per CPU")
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parser.add_argument("--aes-instruction", default=None, help="Enable AES instruction acceleration.")
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parser.add_argument("--aes-instruction", default=None, help="Enable AES instruction acceleration.")
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parser.add_argument("--without-out-of-order-decoder", action='store_true', help="Reduce area at cost of peripheral access speed")
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parser.add_argument("--without-out-of-order-decoder", action="store_true", help="Reduce area at cost of peripheral access speed")
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parser.add_argument("--with-wishbone-memory" , action='store_true', help="Disable native litedram interface")
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parser.add_argument("--with-wishbone-memory" , action="store_true", help="Disable native LiteDRAM interface")
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@staticmethod
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@staticmethod
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def args_read(args):
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def args_read(args):
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@ -76,17 +76,17 @@ class VexRiscvSMP(CPU):
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VexRiscvSMP.dcache_ways = 2
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VexRiscvSMP.dcache_ways = 2
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VexRiscvSMP.icache_ways = 2
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VexRiscvSMP.icache_ways = 2
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VexRiscvSMP.coherent_dma = True
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VexRiscvSMP.coherent_dma = True
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if(args.with_coherent_dma): VexRiscvSMP.coherent_dma = bool(True)
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if(args.with_coherent_dma): VexRiscvSMP.coherent_dma = bool(True)
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if(args.without_coherent_dma): VexRiscvSMP.coherent_dma = bool(False)
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if(args.without_coherent_dma): VexRiscvSMP.coherent_dma = bool(False)
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if(args.dcache_width): VexRiscvSMP.dcache_width = int(args.dcache_width)
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if(args.dcache_width): VexRiscvSMP.dcache_width = int(args.dcache_width)
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if(args.icache_width): VexRiscvSMP.icache_width = int(args.icache_width)
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if(args.icache_width): VexRiscvSMP.icache_width = int(args.icache_width)
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if(args.dcache_size): VexRiscvSMP.dcache_size = int(args.dcache_size)
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if(args.dcache_size): VexRiscvSMP.dcache_size = int(args.dcache_size)
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if(args.icache_size): VexRiscvSMP.icache_size = int(args.icache_size)
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if(args.icache_size): VexRiscvSMP.icache_size = int(args.icache_size)
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if(args.dcache_ways): VexRiscvSMP.dcache_ways = int(args.dcache_ways)
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if(args.dcache_ways): VexRiscvSMP.dcache_ways = int(args.dcache_ways)
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if(args.icache_ways): VexRiscvSMP.icache_ways = int(args.icache_ways)
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if(args.icache_ways): VexRiscvSMP.icache_ways = int(args.icache_ways)
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if(args.aes_instruction): VexRiscvSMP.aes_instruction = bool(args.aes_instruction)
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if(args.aes_instruction): VexRiscvSMP.aes_instruction = bool(args.aes_instruction)
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if(args.without_out_of_order_decoder): VexRiscvSMP.out_of_order_decoder = False
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if(args.without_out_of_order_decoder): VexRiscvSMP.out_of_order_decoder = False
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if(args.with_wishbone_memory): VexRiscvSMP.wishbone_memory = True
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if(args.with_wishbone_memory): VexRiscvSMP.wishbone_memory = True
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@property
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@property
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@ -120,12 +120,11 @@ class VexRiscvSMP(CPU):
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f"Dw{VexRiscvSMP.dcache_width}" \
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f"Dw{VexRiscvSMP.dcache_width}" \
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f"Ds{VexRiscvSMP.dcache_size}" \
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f"Ds{VexRiscvSMP.dcache_size}" \
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f"Dy{VexRiscvSMP.dcache_ways}" \
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f"Dy{VexRiscvSMP.dcache_ways}" \
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"_" \
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f"{'_'+ldw if not VexRiscvSMP.wishbone_memory else ''}" \
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f"{ldw if not VexRiscvSMP.wishbone_memory else ''}" \
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f"{'_Cdma' if VexRiscvSMP.coherent_dma else ''}" \
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f"{'_Cdma' if VexRiscvSMP.coherent_dma else ''}" \
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f"{'_Aes' if VexRiscvSMP.aes_instruction else ''}" \
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f"{'_Aes' if VexRiscvSMP.aes_instruction else ''}"\
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f"{'_Ood' if VexRiscvSMP.out_of_order_decoder else ''}" \
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f"{'_Ood' if VexRiscvSMP.out_of_order_decoder else ''}"\
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f"{'_Wm' if VexRiscvSMP.wishbone_memory else ''}"
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f"{'_Wm' if VexRiscvSMP.wishbone_memory else ''}"
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@staticmethod
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@staticmethod
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def generate_default_configs():
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def generate_default_configs():
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@ -205,7 +204,7 @@ class VexRiscvSMP(CPU):
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gen_args.append(f"--wishbone-memory={VexRiscvSMP.wishbone_memory}")
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gen_args.append(f"--wishbone-memory={VexRiscvSMP.wishbone_memory}")
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gen_args.append(f"--netlist-name={VexRiscvSMP.cluster_name}")
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gen_args.append(f"--netlist-name={VexRiscvSMP.cluster_name}")
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gen_args.append(f"--netlist-directory={vdir}")
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gen_args.append(f"--netlist-directory={vdir}")
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cmd = 'cd {path} && sbt "runMain vexriscv.demo.smp.VexRiscvLitexSmpClusterCmdGen {args}"'.format(path=os.path.join(vdir, "ext", "VexRiscv"), args=" ".join(gen_args))
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cmd = 'cd {path} && sbt "runMain vexriscv.demo.smp.VexRiscvLitexSmpClusterCmdGen {args}"'.format(path=os.path.join(vdir, "ext", "VexRiscv"), args=" ".join(gen_args))
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os.system(cmd)
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os.system(cmd)
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